From patchwork Wed Sep 5 09:41:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abhishek Goel X-Patchwork-Id: 966284 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 424zJ04mghz9s3Z for ; Wed, 5 Sep 2018 19:42:08 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.vnet.ibm.com Received: from lists.ozlabs.org (unknown [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 424zJ03K0JzF37D for ; Wed, 5 Sep 2018 19:42:08 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.vnet.ibm.com X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=none (mailfrom) smtp.mailfrom=linux.vnet.ibm.com (client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com; envelope-from=huntbag@linux.vnet.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.vnet.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 424zHt1MlvzF378 for ; Wed, 5 Sep 2018 19:42:01 +1000 (AEST) Received: from pps.filterd (m0098413.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id w859dH1m051538 for ; Wed, 5 Sep 2018 05:41:58 -0400 Received: from e06smtp01.uk.ibm.com (e06smtp01.uk.ibm.com [195.75.94.97]) by mx0b-001b2d01.pphosted.com with ESMTP id 2maa0n01v5-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 05 Sep 2018 05:41:58 -0400 Received: from localhost by e06smtp01.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Wed, 5 Sep 2018 10:41:55 +0100 Received: from d06av21.portsmouth.uk.ibm.com (d06av21.portsmouth.uk.ibm.com [9.149.105.232]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w859fsTT42598430 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 5 Sep 2018 09:41:54 GMT Received: from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B9C9C5204E; Wed, 5 Sep 2018 12:41:46 +0100 (BST) Received: from ltc-wspoon6.aus.stglabs.ibm.com (unknown [9.40.193.95]) by d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTP id B657D5204F; Wed, 5 Sep 2018 12:41:45 +0100 (BST) From: Abhishek Goel To: skiboot@lists.ozlabs.org, stewart@linux.vnet.ibm.com Date: Wed, 5 Sep 2018 04:41:44 -0500 X-Mailer: git-send-email 2.17.0 X-TM-AS-GCONF: 00 x-cbid: 18090509-4275-0000-0000-000002B58D2D X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18090509-4276-0000-0000-000037BEA59E Message-Id: <20180905094144.11211-1-huntbag@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-09-05_05:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=2 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1807170000 definitions=main-1809050103 Subject: [Skiboot] [PATCH v7] power-mgmt : occ : Add 'freq-domain-mask' DT property X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ego@linux.vnet.ibm.com MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Add a new device-tree property freq-domain-indicator to define group of CPUs which would share same frequency. This property has been added under power-mgmt node. It is a bitmask. Bitwise AND is taken between this bitmask value and PIR of cpu. All the CPUs lying in the same frequency domain will have same result for AND. For example, For POWER9, 0xFFF0 indicates quad wide frequency domain. Taking AND with the PIR of CPUs will yield us frequency domain which is quad wise distribution as last 4 bits have been masked which represent the cores. Similarly, 0xFFF4 will represent core wide frequency domain for P9. Also, Add a new device-tree property domain-runs-at which will denote the strategy OCC is using to change the frequency of a frequency-domain. There can be two strategy - FREQ_MOST_RECENTLY_SET and FREQ_MAX_IN_DOMAIN. Signed-off-by: Abhishek Goel --- v6->v7 : * Add "domain-runs-at" DT node and documented it v5->v6 : * Removed "p9-occ-quirk" and "freq-domain-v1" v4->v5 : * Added documentation for compatibility flags. v3->v4 : * Added compatibility string "p9-occ-quirk" v2->v3 : * Added compatibility string "freq-domain-v1" v1->v2 : * Handled errors if device tree node creation failed. doc/device-tree/ibm,opal/power-mgt/occ.rst | 37 ++++++++++++++++++++++ hw/occ.c | 27 ++++++++++++++++ 2 files changed, 64 insertions(+) diff --git a/doc/device-tree/ibm,opal/power-mgt/occ.rst b/doc/device-tree/ibm,opal/power-mgt/occ.rst index d13a62ba..18da3acb 100644 --- a/doc/device-tree/ibm,opal/power-mgt/occ.rst +++ b/doc/device-tree/ibm,opal/power-mgt/occ.rst @@ -37,3 +37,40 @@ ibm,pstate-vcss ibm,pstate-vdds These properties list a voltage-identifier of each of the pstates listed in ibm,pstate-ids for the Vcs and Vdd values used for that pstate in that chip. Each VID is a single byte. + +ibm,opal/power-mgt/freq-domain-mask +----------------------------------- + +This property is a bitmask which will have different value depending upon the +generation of the processor. Frequency domain would indicate group of CPUs +which would share same frequency. Bitwise AND is taken between this bitmask +value and PIR of cpu. All the CPUs lying in the same frequency domain will have +same result for AND. Thus frequency management can be done based on frequency +domain. A frequency domain may be a core or a quad, etc depending upon the +generation of the processor. + +For example, for POWER8 0xFFF8 indicates core wide frequency domain. Taking AND +with the PIR of CPUs will yield us a frequency domain which is core wide +distribution as last 3 bits have been masked which represent the threads. + +For POWER9, 0xFFF0 indicates quad wide frequency domain. Taking AND with +the PIR of CPUs will yield us frequency domain which is quad wise +distribution as last 4 bits have been masked which represent the cores. + +ibm,opal/power-mgt/domain-runs-at +--------------------------------- + +There are two strategies in which the OCC can change the frequency of the cores +in the quad on P9. +1) FREQ_MAX_IN_DOMAIN : the OCC sets the frequency of the quad to the maximal +value requested by the component cores. +2) FREQ_MOST_RECENTLY_SET : the OCC sets the frequency of the quad to the most +recent frequency value requested by the CPUs in the quad + +In case of P8, the domain is the core and the strategy by default is +FREQ_MOST_RECENTLY_SET since the PMCRs of the threads in the core are mirrored. +However on P9, the domain is quad and the strategy is FREQ_MAX_IN_DOMAIN since +each core has its own PMCR. + +domain-runs-at denotes the strategy which OCC is using to change the frequency +of a frequency domain. diff --git a/hw/occ.c b/hw/occ.c index 29eb4bd6..a29f75e1 100644 --- a/hw/occ.c +++ b/hw/occ.c @@ -48,6 +48,12 @@ #define MAX_OPAL_CMD_DATA_LENGTH 4090 #define MAX_OCC_RSP_DATA_LENGTH 8698 +#define P8_PIR_CORE_MASK 0xFFF8 +#define P9_PIR_CORE_MASK 0xFFF4 +#define P9_PIR_QUAD_MASK 0xFFF0 +#define FREQ_MAX_IN_DOMAIN 0 +#define FREQ_MOST_RECENTLY_SET 1 + /** * OCC-OPAL Shared Memory Region * @@ -489,6 +495,15 @@ static bool add_cpu_pstate_properties(int *pstate_nom) u8 nr_pstates; bool ultra_turbo_supported; int i, major, minor; + u8 domain_runs_at; + u32 freq_domain_mask; + + /* TODO Firmware plumbing required so as to have two modes to set + * PMCR based on max in domain or most recently used. As of today, + * it is always max in domain for P9. + */ + domain_runs_at = 0; + freq_domain_mask = 0; prlog(PR_DEBUG, "OCC: CPU pstate state device tree init\n"); @@ -661,6 +676,16 @@ static bool add_cpu_pstate_properties(int *pstate_nom) return false; } + if (proc_gen == proc_gen_p8) { + freq_domain_mask = P8_PIR_CORE_MASK; + domain_runs_at = FREQ_MOST_RECENTLY_SET; + } else if (proc_gen == proc_gen_p9) { + if (domain_runs_at == FREQ_MAX_IN_DOMAIN) + freq_domain_mask = P9_PIR_CORE_MASK; + else if (domain_runs_at == FREQ_MOST_RECENTLY_SET) + freq_domain_mask = P9_PIR_QUAD_MASK; + } + /* Add the device-tree entries */ dt_add_property(power_mgt, "ibm,pstate-ids", dt_id, nr_pstates * sizeof(u32)); @@ -669,6 +694,8 @@ static bool add_cpu_pstate_properties(int *pstate_nom) dt_add_property_cells(power_mgt, "ibm,pstate-min", pmin); dt_add_property_cells(power_mgt, "ibm,pstate-nominal", pnom); dt_add_property_cells(power_mgt, "ibm,pstate-max", pmax); + dt_add_property_cells(power_mgt, "freq-domain-mask", freq_domain_mask); + dt_add_property_cells(power_mgt, "domain-runs-at", domain_runs_at); free(dt_freq); free(dt_id);