From patchwork Tue Sep 4 08:43:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: shun-chih.yu@mediatek.com X-Patchwork-Id: 965832 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=mediatek.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 424L3d2tbgz9s7T for ; Tue, 4 Sep 2018 18:44:13 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727339AbeIDNIT (ORCPT ); Tue, 4 Sep 2018 09:08:19 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:61382 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726061AbeIDNIS (ORCPT ); Tue, 4 Sep 2018 09:08:18 -0400 X-UUID: b6852eb8c0dd4244bd1c716c74b5ab18-20180904 Received: from mtkcas09.mediatek.inc [(172.21.101.178)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1211274827; Tue, 04 Sep 2018 16:44:00 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs02n1.mediatek.inc (172.21.101.77) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Tue, 4 Sep 2018 16:43:57 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Tue, 4 Sep 2018 16:43:57 +0800 From: To: Sean Wang , Vinod Koul , Rob Herring , Matthias Brugger , Dan Williams CC: , , , , , , Shun-Chih Yu Subject: [PATCH 1/2] dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings Date: Tue, 4 Sep 2018 16:43:45 +0800 Message-ID: <1536050626-21927-2-git-send-email-shun-chih.yu@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1536050626-21927-1-git-send-email-shun-chih.yu@mediatek.com> References: <1536050626-21927-1-git-send-email-shun-chih.yu@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Shun-Chih Yu Document the devicetree bindings for MediaTek Command-Queue DMA controller which could be found on MT6765 SoC or other similar Mediatek SoCs. Signed-off-by: Shun-Chih Yu --- .../devicetree/bindings/dma/mtk-cqdma.txt | 31 ++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/mtk-cqdma.txt diff --git a/Documentation/devicetree/bindings/dma/mtk-cqdma.txt b/Documentation/devicetree/bindings/dma/mtk-cqdma.txt new file mode 100644 index 0000000..fb12927 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/mtk-cqdma.txt @@ -0,0 +1,31 @@ +MediaTek Command-Queue DMA Controller +================================== + +Required properties: + +- compatible: Must be "mediatek,mt6765-cqdma" for MT6765. +- reg: Should contain the base address and length for each channel. +- interrupts: Should contain references to the interrupts for each channel. +- clocks: Should be the clock specifiers corresponding to the entry in + clock-names property. +- clock-names: Should contain "cqdma" entries. +- dma-channels: The number of DMA channels supported by the controller. +- dma-requests: The number of DMA request supported by the controller. +- #dma-cells: The length of the DMA specifier, must be <1>. This one cell + in dmas property of a client device represents the channel + number. +Example: + + cqdma: dma-controller@10212000 { + compatible = "mediatek,mt6765-cqdma"; + reg = <0 0x10212000 0 0x1000>; + interrupts = , + ; + clocks = <&infracfg CLK_IFR_CQ_DMA>; + clock-names = "cqdma"; + dma-channels = <2>; + dma-requests = <32>; + #dma-cells = <1>; + }; + +DMA clients must use the format described in dma/dma.txt file.