From patchwork Fri May 20 03:33:53 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 96520 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 595EDB71C9 for ; Fri, 20 May 2011 13:34:13 +1000 (EST) Received: from localhost ([::1]:55455 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QNGTa-0000QK-6W for incoming@patchwork.ozlabs.org; Thu, 19 May 2011 23:34:10 -0400 Received: from eggs.gnu.org ([140.186.70.92]:35383) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QNGTS-0000Q7-LD for qemu-devel@nongnu.org; Thu, 19 May 2011 23:34:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QNGTQ-0000aJ-8X for qemu-devel@nongnu.org; Thu, 19 May 2011 23:34:02 -0400 Received: from ozlabs.org ([203.10.76.45]:49034) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QNGTP-0000aA-PV for qemu-devel@nongnu.org; Thu, 19 May 2011 23:34:00 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id BDE76B71D2; Fri, 20 May 2011 13:33:57 +1000 (EST) From: David Gibson To: agraf@suse.de, qemu-devel@nongnu.org Date: Fri, 20 May 2011 13:33:53 +1000 Message-Id: <1305862433-12204-1-git-send-email-david@gibson.dropbear.id.au> X-Mailer: git-send-email 1.7.4.4 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) X-Received-From: 203.10.76.45 Cc: andreas.farber@web.de, kennethsalerno@yahoo.com, paulus@samba.org Subject: [Qemu-devel] [PATCH] Fix a bug in mtsr/mtsrin emulation on ppc64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Early ppc64 CPUs include a hack to partially simulate the ppc32 segment registers, by translating writes to them into writes to the SLB. This is not used by any current Linux kernel, but it is used by the openbios used in the qemu mac99 model. Commit 81762d6dd0d430d87024f2c83e9c4dcc4329fb7d, cleaning up the SLB handling introduced a bug in this code, breaking the openbios currently in qemu. Specifically, there was an off by one error bitshuffling the register format used by mtsr into the format needed for the SLB load, causing the flag bits to end up in the wrong place. This caused the storage keys to be wrong under openbios, meaning that the translation code incorrectly thought a legitimate access was a permission violation. This patch fixes the bug, at the same time it fixes some build bug in the MMU debugging code (only exposed when DEBUG_MMU is enabled). Signed-off-by: David Gibson --- target-ppc/helper.c | 9 ++++----- 1 files changed, 4 insertions(+), 5 deletions(-) diff --git a/target-ppc/helper.c b/target-ppc/helper.c index 4238be6..4700632 100644 --- a/target-ppc/helper.c +++ b/target-ppc/helper.c @@ -606,7 +606,7 @@ static inline int _find_pte(CPUState *env, mmu_ctx_t *ctx, int is_64b, int h, r = pte64_check(ctx, pte0, pte1, h, rw, type); LOG_MMU("Load pte from " TARGET_FMT_lx " => " TARGET_FMT_lx " " TARGET_FMT_lx " %d %d %d " TARGET_FMT_lx "\n", - pteg_base + (i * 16), pte0, pte1, (int)(pte0 & 1), h, + pteg_off + (i * 16), pte0, pte1, (int)(pte0 & 1), h, (int)((pte0 >> 1) & 1), ctx->ptem); } else #endif @@ -621,7 +621,7 @@ static inline int _find_pte(CPUState *env, mmu_ctx_t *ctx, int is_64b, int h, r = pte32_check(ctx, pte0, pte1, h, rw, type); LOG_MMU("Load pte from " TARGET_FMT_lx " => " TARGET_FMT_lx " " TARGET_FMT_lx " %d %d %d " TARGET_FMT_lx "\n", - pteg_base + (i * 8), pte0, pte1, (int)(pte0 >> 31), h, + pteg_off + (i * 8), pte0, pte1, (int)(pte0 >> 31), h, (int)((pte0 >> 6) & 1), ctx->ptem); } switch (r) { @@ -918,8 +918,7 @@ static inline int get_segment(CPUState *env, mmu_ctx_t *ctx, if (eaddr != 0xEFFFFFFF) LOG_MMU("1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx " vsid=" TARGET_FMT_lx " api=" TARGET_FMT_lx - " hash=" TARGET_FMT_plx " pg_addr=" - TARGET_FMT_plx "\n", env->htab_base, + " hash=" TARGET_FMT_plx "\n", env->htab_base, env->htab_mask, vsid, ctx->ptem, ctx->hash[1]); ret2 = find_pte(env, ctx, 1, rw, type, target_page_bits); @@ -2140,7 +2139,7 @@ void ppc_store_sr (CPUPPCState *env, int srnum, target_ulong value) /* VSID = VSID */ rs |= (value & 0xfffffff) << 12; /* flags = flags */ - rs |= ((value >> 27) & 0xf) << 9; + rs |= ((value >> 27) & 0xf) << 8; ppc_store_slb(env, rb, rs); } else