From patchwork Thu May 19 20:23:50 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex X-Patchwork-Id: 96454 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id B15C3B718A for ; Fri, 20 May 2011 06:28:45 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7FE28280E8; Thu, 19 May 2011 22:28:42 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id twbJE44oy7mc; Thu, 19 May 2011 22:28:42 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 2BB5B280F3; Thu, 19 May 2011 22:28:39 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 95E77280F3 for ; Thu, 19 May 2011 22:28:36 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 938GC4BgJdhk for ; Thu, 19 May 2011 22:28:35 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail.dawning.com (mail.dawning.com [63.247.149.203]) by theia.denx.de (Postfix) with ESMTP id 13DA3280E8 for ; Thu, 19 May 2011 22:28:33 +0200 (CEST) Received: from victoria.dawning.com by mail.dawning.com (MDaemon PRO v9.5.4) with ESMTP id 63-md50000008748.msg for ; Thu, 19 May 2011 16:28:31 -0400 Message-ID: <4DD57C56.9050904@dawning.com> Date: Thu, 19 May 2011 16:23:50 -0400 From: Alex Waterman User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.15) Gecko/20110307 Fedora/3.1.9-0.39.b3pre.fc14 Thunderbird/3.1.9 MIME-Version: 1.0 To: Wolfgang Denk References: <4DD56FCF.2010306@dawning.com> <20110519195009.AD4121491B0E@gemini.denx.de> In-Reply-To: <20110519195009.AD4121491B0E@gemini.denx.de> X-Authenticated-Sender: awaterman@dawning.com X-Spam-Processed: mail.dawning.com, Thu, 19 May 2011 16:28:31 -0400 (not processed: message from trusted or authenticated source) X-Return-Path: awaterman@dawning.com X-Envelope-From: awaterman@dawning.com X-MDaemon-Deliver-To: u-boot@lists.denx.de Cc: u-boot@lists.denx.de Subject: Re: [U-Boot] [PATCH] [NAND] Fixes 16bit NAND support with the NDFC X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Alex Waterman Date: Thu, 19 May 2011 15:08:36 -0400 Subject: [PATCH] [NAND] Fixes 16bit NAND support with the NDFC This patch adds support for 16 bit NAND devices attached to the NDFC on ppc4xx processors. Two config entries were added: CONFIG_SYS_NDFC_16 - Setting this tells the NDFC that a 16 bit device is attached. CONFIG_SYS_NDFC_EBC0_CFG - This is for the External Bus Controller configuration register. Also, a new ndfc_read_byte() function was added which does not first convert the data to little endian. The NAND SPL was also modified to do 16bit bad block testing when a 16 bit chip is being used. Signed-off-by: Alex Waterman Cc: Scott Wood Cc: Stefan Roese --- README | 8 ++++++++ drivers/mtd/nand/ndfc.c | 34 +++++++++++++++++++++++++++++----- nand_spl/nand_boot.c | 11 ++++++++--- 3 files changed, 45 insertions(+), 8 deletions(-) Here is the new patch with the README updated to reflect the config options added. diff --git a/README b/README index 6f3748d..3ede798 100644 --- a/README +++ b/README @@ -2912,6 +2912,14 @@ Low Level (hardware related) configuration options: - CONFIG_SYS_SRIOn_MEM_SIZE: Size of SRIO port 'n' memory region +- CONFIG_SYS_NDFC_16 + Defined to tell the NDFC that the NAND chip is using a + 16 bit bus. + +- CONFIG_SYS_NDFC_EBC0_CFG + Sets the EBC0_CFG register for the NDFC. If not defined + a default value will be used. + - CONFIG_SPD_EEPROM Get DDR timing information from an I2C EEPROM. Common with pluggable memory modules such as SODIMMs diff --git a/drivers/mtd/nand/ndfc.c b/drivers/mtd/nand/ndfc.c index 0729e0c..b533474 100644 --- a/drivers/mtd/nand/ndfc.c +++ b/drivers/mtd/nand/ndfc.c @@ -37,6 +37,13 @@ #include #include +#ifndef CONFIG_SYS_NAND_BCR +#define CONFIG_SYS_NAND_BCR 0x80002222 +#endif +#ifndef CONFIG_SYS_NDFC_EBC0_CFG +#define CONFIG_SYS_NDFC_EBC0_CFG 0xb8400000 +#endif + /* * We need to store the info, which chip-select (CS) is used for the * chip number. For example on Sequoia NAND chip #0 uses @@ -140,11 +147,23 @@ static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len return 0; } -#endif /* #ifndef CONFIG_NAND_SPL */ -#ifndef CONFIG_SYS_NAND_BCR -#define CONFIG_SYS_NAND_BCR 0x80002222 -#endif +/* + * Read a byte from the NDFC. + */ +static uint8_t ndfc_read_byte(struct mtd_info *mtd) +{ + + struct nand_chip *chip = mtd->priv; + + if (chip->options & NAND_BUSWIDTH_16) + return (uint8_t) readw(chip->IO_ADDR_R); + else + return readb(chip->IO_ADDR_R); + +} + +#endif /* #ifndef CONFIG_NAND_SPL */ void board_nand_select_device(struct nand_chip *nand, int chip) { @@ -198,16 +217,21 @@ int board_nand_init(struct nand_chip *nand) nand->ecc.bytes = 3; nand->select_chip = ndfc_select_chip; +#ifdef CONFIG_SYS_NDFC_16BIT + nand->options |= NAND_BUSWIDTH_16; +#endif + #ifndef CONFIG_NAND_SPL nand->write_buf = ndfc_write_buf; nand->verify_buf = ndfc_verify_buf; + nand->read_byte = ndfc_read_byte; chip++; #else /* * Setup EBC (CS0 only right now) */ - mtebc(EBC0_CFG, 0xb8400000); + mtebc(EBC0_CFG, CONFIG_SYS_NDFC_EBC0_CFG); mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR); mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP); diff --git a/nand_spl/nand_boot.c b/nand_spl/nand_boot.c index 9545a9a..4683c7c 100644 --- a/nand_spl/nand_boot.c +++ b/nand_spl/nand_boot.c @@ -122,10 +122,15 @@ static int nand_is_bad_block(struct mtd_info *mtd, int block) nand_command(mtd, block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB); /* - * Read one byte + * Read one byte (or two if it's a 16 bit chip). */ - if (readb(this->IO_ADDR_R) != 0xff) - return 1; + if (this->options & NAND_BUSWIDTH_16) { + if (readw(this->IO_ADDR_R) != 0xffff) + return 1; + } else { + if (readb(this->IO_ADDR_R) != 0xff) + return 1; + } return 0; }