Patchwork [U-Boot,NAND] Fixes 16bit NAND support with the NDFC

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Submitter Alex
Date May 19, 2011, 7:30 p.m.
Message ID <4DD56FCF.2010306@dawning.com>
Download mbox | patch
Permalink /patch/96450/
State Changes Requested
Headers show

Comments

Alex - May 19, 2011, 7:30 p.m.
From ad2238044b9abc5a2094096219a1256a8ad091b0 Mon Sep 17 00:00:00 2001
From: Alex Waterman <awaterman@dawning.com>
Date: Thu, 19 May 2011 15:08:36 -0400
Subject: [PATCH] [NAND] Fixes 16bit NAND support with the NDFC

This patch adds support for 16 bit NAND devices attached to the
NDFC on ppc4xx processors. Two config entries were added:

  CONFIG_SYS_NDFC_16        - Setting this tells the NDFC that a
  			      16 bit device is attached.
  CONFIG_SYS_NDFC_EBC0_CFG  - This is for the External Bus
  			      Controller configuration register.

Also, a new ndfc_read_byte() function was added which does not
first convert the data to little endian.

The NAND SPL was also modified to do 16bit bad block testing
when a 16 bit chip is being used.

Signed-off-by: Alex Waterman <awaterman@dawning.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Stefan Roese <sr@denx.de>
---
 drivers/mtd/nand/ndfc.c |   34 +++++++++++++++++++++++++++++-----
 nand_spl/nand_boot.c    |   11 ++++++++---
 2 files changed, 37 insertions(+), 8 deletions(-)
Wolfgang Denk - May 19, 2011, 7:50 p.m.
Dear Alex Waterman,

In message <4DD56FCF.2010306@dawning.com> you wrote:
> From ad2238044b9abc5a2094096219a1256a8ad091b0 Mon Sep 17 00:00:00 2001
> From: Alex Waterman <awaterman@dawning.com>
> Date: Thu, 19 May 2011 15:08:36 -0400
> Subject: [PATCH] [NAND] Fixes 16bit NAND support with the NDFC
> 
> This patch adds support for 16 bit NAND devices attached to the
> NDFC on ppc4xx processors. Two config entries were added:
> 
>   CONFIG_SYS_NDFC_16        - Setting this tells the NDFC that a
>   			      16 bit device is attached.
>   CONFIG_SYS_NDFC_EBC0_CFG  - This is for the External Bus
>   			      Controller configuration register.
> 
> Also, a new ndfc_read_byte() function was added which does not
> first convert the data to little endian.
> 
> The NAND SPL was also modified to do 16bit bad block testing
> when a 16 bit chip is being used.
> 
> Signed-off-by: Alex Waterman <awaterman@dawning.com>
> Cc: Scott Wood <scottwood@freescale.com>
> Cc: Stefan Roese <sr@denx.de>
> ---
>  drivers/mtd/nand/ndfc.c |   34 +++++++++++++++++++++++++++++-----
>  nand_spl/nand_boot.c    |   11 ++++++++---
>  2 files changed, 37 insertions(+), 8 deletions(-)

Please document the new CONFIG_SYS_* options in the README.

Best regards,

Wolfgang Denk

Patch

diff --git a/drivers/mtd/nand/ndfc.c b/drivers/mtd/nand/ndfc.c
index 0729e0c..b533474 100644
--- a/drivers/mtd/nand/ndfc.c
+++ b/drivers/mtd/nand/ndfc.c
@@ -37,6 +37,13 @@ 
 #include <asm/io.h>
 #include <asm/ppc4xx.h>
 
+#ifndef CONFIG_SYS_NAND_BCR
+#define CONFIG_SYS_NAND_BCR 0x80002222
+#endif
+#ifndef CONFIG_SYS_NDFC_EBC0_CFG
+#define CONFIG_SYS_NDFC_EBC0_CFG 0xb8400000
+#endif
+
 /*
  * We need to store the info, which chip-select (CS) is used for the
  * chip number. For example on Sequoia NAND chip #0 uses
@@ -140,11 +147,23 @@  static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len
 
 	return 0;
 }
-#endif /* #ifndef CONFIG_NAND_SPL */
 
-#ifndef CONFIG_SYS_NAND_BCR
-#define CONFIG_SYS_NAND_BCR 0x80002222
-#endif
+/*
+ * Read a byte from the NDFC.
+ */
+static uint8_t ndfc_read_byte(struct mtd_info *mtd)
+{
+
+	struct nand_chip *chip = mtd->priv;
+
+	if (chip->options & NAND_BUSWIDTH_16)
+		return (uint8_t) readw(chip->IO_ADDR_R);
+	else
+		return readb(chip->IO_ADDR_R);
+
+}
+
+#endif /* #ifndef CONFIG_NAND_SPL */
 
 void board_nand_select_device(struct nand_chip *nand, int chip)
 {
@@ -198,16 +217,21 @@  int board_nand_init(struct nand_chip *nand)
 	nand->ecc.bytes = 3;
 	nand->select_chip = ndfc_select_chip;
 
+#ifdef CONFIG_SYS_NDFC_16BIT
+	nand->options |= NAND_BUSWIDTH_16;
+#endif
+
 #ifndef CONFIG_NAND_SPL
 	nand->write_buf  = ndfc_write_buf;
 	nand->verify_buf = ndfc_verify_buf;
+	nand->read_byte = ndfc_read_byte;
 
 	chip++;
 #else
 	/*
 	 * Setup EBC (CS0 only right now)
 	 */
-	mtebc(EBC0_CFG, 0xb8400000);
+	mtebc(EBC0_CFG, CONFIG_SYS_NDFC_EBC0_CFG);
 
 	mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR);
 	mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP);
diff --git a/nand_spl/nand_boot.c b/nand_spl/nand_boot.c
index 9545a9a..4683c7c 100644
--- a/nand_spl/nand_boot.c
+++ b/nand_spl/nand_boot.c
@@ -122,10 +122,15 @@  static int nand_is_bad_block(struct mtd_info *mtd, int block)
 	nand_command(mtd, block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);
 
 	/*
-	 * Read one byte
+	 * Read one byte (or two if it's a 16 bit chip).
 	 */
-	if (readb(this->IO_ADDR_R) != 0xff)
-		return 1;
+	if (this->options & NAND_BUSWIDTH_16) {
+		if (readw(this->IO_ADDR_R) != 0xffff)
+			return 1;
+	} else {
+		if (readb(this->IO_ADDR_R) != 0xff)
+			return 1;
+	}
 
 	return 0;
 }