Message ID | 20180831103816.13479-3-clg@kaod.org |
---|---|
State | New |
Headers | show |
Series | aspeed: misc fixes and enhancements (SMC) | expand |
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index bb9590f1aed1..f2d64e45511a 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -105,7 +105,7 @@ static const AspeedBoardConfig aspeed_boards[] = { [AST2500_EVB] = { .soc_name = "ast2500-a1", .hw_strap1 = AST2500_EVB_HW_STRAP1, - .fmc_model = "n25q256a", + .fmc_model = "w25q256", .spi_model = "mx25l25635e", .num_cs = 1, .i2c_init = ast2500_evb_i2c_init,
The AST2500 evb is shipped with a W25Q256 which has a non volatile bit to make the chip operate in 4 Byte address mode at power up. This should be an interesting feature to model as it will exercise a bit more the SMC controllers and MMIO execution at boot time. Signed-off-by: Cédric Le Goater <clg@kaod.org> --- hw/arm/aspeed.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)