[v2,2/3] dt-bindings: net: dsa: Document B53 SRAB interrupts and registers
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Message ID 20180828175420.7992-3-f.fainelli@gmail.com
State Changes Requested
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Series
  • ARM: NSP updates to support switch interrupts/SFP
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Commit Message

Florian Fainelli Aug. 28, 2018, 5:54 p.m. UTC
Document the Broadcom roboswitch Switch Register Access Block interrupt
lines and additional register base addresses for port mux configuration
and SGMII status/configuration registers.

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
 .../devicetree/bindings/net/dsa/b53.txt       | 23 +++++++++++++++++++
 1 file changed, 23 insertions(+)

Comments

Rob Herring Aug. 29, 2018, 1:05 a.m. UTC | #1
On Tue, Aug 28, 2018 at 10:54:19AM -0700, Florian Fainelli wrote:
> Document the Broadcom roboswitch Switch Register Access Block interrupt
> lines and additional register base addresses for port mux configuration
> and SGMII status/configuration registers.
> 
> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
> ---
>  .../devicetree/bindings/net/dsa/b53.txt       | 23 +++++++++++++++++++
>  1 file changed, 23 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/net/dsa/b53.txt b/Documentation/devicetree/bindings/net/dsa/b53.txt
> index 1811e1972a7a..5f1029e853b8 100644
> --- a/Documentation/devicetree/bindings/net/dsa/b53.txt
> +++ b/Documentation/devicetree/bindings/net/dsa/b53.txt
> @@ -46,6 +46,29 @@ Required properties:
>        "brcm,bcm6328-switch"
>        "brcm,bcm6368-switch" and the mandatory "brcm,bcm63xx-switch"
>  
> +Required properties for BCM585xx/586xx/88312 SoCs:
> +
> + - reg: a total of 3 register base addresses, the first one must be the
> +   Switch Register Access block base, the second is the port 5/4 mux
> +   configuration register and the third one is the SGMII configuration
> +   and status register base address.
> +
> + - interrupts: a total of 13 interrupts must be specified, in the following
> +   order: port 0-5, 7-8 link status change, then the integrated PHY interrupt,
> +   then the timestamping interrupt and the sleep timer interrupts for ports
> +   5,7,8.

Bulleted lists would be easier to read.

> +
> +Optional properties for BCM585xx/586xx/88312 SoCs:
> +
> +  - reg-names: a total of 3 names matching the 3 base register address, must
> +    be "srab", "mux_config" and "sgmii_config";

Here too, one per line please.

> +
> +  - interrupt-names: a total of 13 names matching the 13 interrupts specified
> +    must be: "link_state_p0", "link_state_p1", "link_state_p2",
> +    "link_state_p3", "link_state_p4", "link_state_p5", "link_state_p7",
> +    "link_state_p8", "phy", "ts", "imp_sleep_timer_p5", "imp_sleep_timer_p7",
> +    "imp_sleep_timer_p8"
> +
>  See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of additional
>  required and optional properties.
>  
> -- 
> 2.17.1
>

Patch
diff mbox series

diff --git a/Documentation/devicetree/bindings/net/dsa/b53.txt b/Documentation/devicetree/bindings/net/dsa/b53.txt
index 1811e1972a7a..5f1029e853b8 100644
--- a/Documentation/devicetree/bindings/net/dsa/b53.txt
+++ b/Documentation/devicetree/bindings/net/dsa/b53.txt
@@ -46,6 +46,29 @@  Required properties:
       "brcm,bcm6328-switch"
       "brcm,bcm6368-switch" and the mandatory "brcm,bcm63xx-switch"
 
+Required properties for BCM585xx/586xx/88312 SoCs:
+
+ - reg: a total of 3 register base addresses, the first one must be the
+   Switch Register Access block base, the second is the port 5/4 mux
+   configuration register and the third one is the SGMII configuration
+   and status register base address.
+
+ - interrupts: a total of 13 interrupts must be specified, in the following
+   order: port 0-5, 7-8 link status change, then the integrated PHY interrupt,
+   then the timestamping interrupt and the sleep timer interrupts for ports
+   5,7,8.
+
+Optional properties for BCM585xx/586xx/88312 SoCs:
+
+  - reg-names: a total of 3 names matching the 3 base register address, must
+    be "srab", "mux_config" and "sgmii_config";
+
+  - interrupt-names: a total of 13 names matching the 13 interrupts specified
+    must be: "link_state_p0", "link_state_p1", "link_state_p2",
+    "link_state_p3", "link_state_p4", "link_state_p5", "link_state_p7",
+    "link_state_p8", "phy", "ts", "imp_sleep_timer_p5", "imp_sleep_timer_p7",
+    "imp_sleep_timer_p8"
+
 See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of additional
 required and optional properties.