Patchwork [U-Boot,v3,1/4] MX5: Make the weim structure complete

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Submitter Fabio Estevam
Date May 18, 2011, 8:47 p.m.
Message ID <1305751670-30808-1-git-send-email-fabio.estevam@freescale.com>
Download mbox | patch
Permalink /patch/96225/
State Superseded
Headers show

Comments

Fabio Estevam - May 18, 2011, 8:47 p.m.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
Changes since v2:
- Add CS1_BASE_ADDR for MX51
- Add WEIM Registers
 arch/arm/include/asm/arch-mx5/imx-regs.h |  131 ++++++++++++++++++++++++++++--
 1 files changed, 125 insertions(+), 6 deletions(-)

Patch

diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h
index a1849f8..b65b11f 100644
--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
@@ -32,6 +32,7 @@ 
 #define CSD0_BASE_ADDR          0x90000000
 #define CSD1_BASE_ADDR          0xA0000000
 #define NFC_BASE_ADDR_AXI       0xCFFF0000
+#define CS1_BASE_ADDR           0xB8000000
 #elif defined(CONFIG_MX53)
 #define IPU_CTRL_BASE_ADDR      0x18000000
 #define SPBA0_BASE_ADDR         0x50000000
@@ -41,6 +42,7 @@ 
 #define CSD1_BASE_ADDR          0xB0000000
 #define NFC_BASE_ADDR_AXI       0xF7FF0000
 #define IRAM_BASE_ADDR          0xF8000000
+#define CS1_BASE_ADDR           0xF4000000
 #else
 #error "CPU_TYPE not defined"
 #endif
@@ -129,6 +131,90 @@ 
 #define SAHARA_BASE_ADDR	(AIPS2_BASE_ADDR + 0x000F8000)
 
 /*
+ * WEIM CSnGCR1
+ */
+#define CSEN(x)	(x)
+#define SWR(x)		((x) << 1)
+#define SRD(x)		((x) << 2)
+#define MUM(x)		((x) << 3)
+#define WFL(x)		((x) << 4)
+#define RFL(x)		((x) << 5)
+#define CRE(x)		((x) << 6)
+#define CREP(x)	((x) << 7)
+#define BL(x)		(((x) & 0x7) << 8)
+#define WC(x)		((x) << 11)
+#define BCD(x)		(((x) & 0x3) << 12)
+#define BCS(x)		(((x) & 0x3) << 14)
+#define DSZ(x)		(((x) & 0x7) << 16)
+#define SP(x)		((x) << 19)
+#define CSREC(x)	(((x) & 0x7) << 20)
+#define AUS(x)		((x) << 23)
+#define GBC(x)		(((x) & 0x7) << 24)
+#define WP(x)		((x) << 27)
+#define PSZ(x)		(((x) & 0x0f << 28)
+
+/*
+ * WEIM CSnGCR2
+ */
+#define ADH(x)		(((x) & 0x3))
+#define DAPS(x)	(((x) & 0x0f << 4)
+#define DAE(x)		((x) << 8)
+#define DAP(x)		((x) << 9)
+#define MUX16_BYP(x)	((x) << 12)
+
+/*
+ * WEIM CSnRCR1
+ */
+#define RCSN(x)	(((x) & 0x7))
+#define RCSA(x)	(((x) & 0x7) << 4)
+#define OEN(x)		(((x) & 0x7) << 8)
+#define OEA(x)		(((x) & 0x7) << 12)
+#define RADVN(x)	(((x) & 0x7) << 16)
+#define RAL(x)		((x) << 19)
+#define RADVA(x)	(((x) & 0x7) << 20)
+#define RWSC(x)	(((x) & 0x3f) << 24)
+
+/*
+ * WEIM CSnRCR2
+ */
+#define RBEN(x)	(((x) & 0x7))
+#define RBE(x)		((x) << 3)
+#define RBEA(x)	(((x) & 0x7) << 4)
+#define RL(x)		(((x) & 0x3) << 8)
+#define PAT(x)		(((x) & 0x7) << 12)
+#define APR(x)		((x) << 15)
+
+/*
+ * WEIM CSnWCR1
+ */
+#define WCSN(x)	(((x) & 0x7))
+#define WCSA(x)	(((x) & 0x7) << 3)
+#define WEN(x)		(((x) & 0x7) << 6)
+#define WEA(x)		(((x) & 0x7) << 9)
+#define WBEN(x)	(((x) & 0x7) << 12)
+#define WBEA(x)	(((x) & 0x7) << 15)
+#define WADVN(x)	(((x) & 0x7) << 18)
+#define WADVA(x)	(((x) & 0x7) << 21)
+#define WWSC(x)	(((x) & 0x3f) << 24)
+#define WBED1(x)	((x) << 30)
+#define WAL(x)		((x) << 31)
+
+/*
+ * WEIM CSnWCR2
+ */
+#define WBED(x)	(x)
+
+/*
+ * WEIM WCR
+ */
+#define BCM(x)		(x)
+#define GBCD(x)	(((x) & 0x3) << 1)
+#define INTEN(x)	((x) << 4)
+#define INTPOL(x)	((x) << 5)
+#define WDOG_EN(x)	((x) << 8)
+#define WDOG_LIMIT(x)	(((x) & 0x3) << 9)
+
+/*
  * Number of GPIO pins per port
  */
 #define GPIO_NUM_PIN            32
@@ -231,12 +317,45 @@  struct clkctl {
 
 /* WEIM registers */
 struct weim {
-	u32	csgcr1;
-	u32	csgcr2;
-	u32	csrcr1;
-	u32	csrcr2;
-	u32	cswcr1;
-	u32	cswcr2;
+	u32	cs0gcr1;
+	u32	cs0gcr2;
+	u32	cs0rcr1;
+	u32	cs0rcr2;
+	u32	cs0wcr1;
+	u32	cs0wcr2;
+	u32	cs1gcr1;
+	u32	cs1gcr2;
+	u32	cs1rcr1;
+	u32	cs1rcr2;
+	u32	cs1wcr1;
+	u32	cs1wcr2;
+	u32	cs2gcr1;
+	u32	cs2gcr2;
+	u32	cs2rcr1;
+	u32	cs2rcr2;
+	u32	cs2wcr1;
+	u32	cs2wcr2;
+	u32	cs3gcr1;
+	u32	cs3gcr2;
+	u32	cs3rcr1;
+	u32	cs3rcr2;
+	u32	cs3wcr1;
+	u32	cs3wcr2;
+	u32	cs4gcr1;
+	u32	cs4gcr2;
+	u32	cs4rcr1;
+	u32	cs4rcr2;
+	u32	cs4wcr1;
+	u32	cs4wcr2;
+	u32	cs5gcr1;
+	u32	cs5gcr2;
+	u32	cs5rcr1;
+	u32	cs5rcr2;
+	u32	cs5wcr1;
+	u32	cs5wcr2;
+	u32	wcr;
+	u32	wiar;
+	u32	ear;
 };
 
 /* GPIO Registers */