From patchwork Fri Aug 24 07:33:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hanjie Lin X-Patchwork-Id: 961716 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amlogic.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41xY0R3wKkz9s4v for ; Fri, 24 Aug 2018 17:32:55 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727604AbeHXLGQ (ORCPT ); Fri, 24 Aug 2018 07:06:16 -0400 Received: from mail-sh2.amlogic.com ([58.32.228.45]:27897 "EHLO mail-sh2.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726818AbeHXLGQ (ORCPT ); Fri, 24 Aug 2018 07:06:16 -0400 Received: from droid10.amlogic.com (10.18.11.213) by mail-sh2.amlogic.com (10.18.11.6) with Microsoft SMTP Server id 15.0.1320.4; Fri, 24 Aug 2018 15:33:00 +0800 From: Hanjie Lin To: Kishon Vijay Abraham I CC: Yue Wang , Hanjie Lin , , , , Kevin Hilman , Carlo Caione , Rob Herring , Yixun Lan , Liang Yang , Jianxin Pan , Qiufang Dai , Jian Hu , Subject: [PATCH v2 1/2] dt-bindings: phy: add DT bindings for Amlogic Meson PCIe Phy controller Date: Fri, 24 Aug 2018 15:33:25 +0800 Message-ID: <1535096006-152091-2-git-send-email-hanjie.lin@amlogic.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1535096006-152091-1-git-send-email-hanjie.lin@amlogic.com> References: <1535096006-152091-1-git-send-email-hanjie.lin@amlogic.com> MIME-Version: 1.0 X-Originating-IP: [10.18.11.213] Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Yue Wang The Meson-PCIE-PHY controller supports the 5-Gbps data rate of the PCI Express Gen 2 specification and is backward compatible with the 2.5-Gbps Gen 1.1 specification with only inferred idle detection supported on Amlogic SoCs. Signed-off-by: Hanjie Lin Signed-off-by: Yue Wang Reviewed-by: Rob Herring --- .../bindings/phy/amlogic,meson-pcie-phy.txt | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/amlogic,meson-pcie-phy.txt diff --git a/Documentation/devicetree/bindings/phy/amlogic,meson-pcie-phy.txt b/Documentation/devicetree/bindings/phy/amlogic,meson-pcie-phy.txt new file mode 100644 index 0000000..e2f0a27 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/amlogic,meson-pcie-phy.txt @@ -0,0 +1,21 @@ +* Amlogic Meson AXG PCIE PHY binding + +Required properties: +- compatible: Should be + - "amlogic,axg-pcie-phy" +- #phys-cells: must be 0 (see phy-bindings.txt in this directory) +- reg: The base address and length of the registers +- resets: phandle to the reset lines +- reset-names: must contain "phy" and "peripheral" + - "phy" PHY reset +Optional properties: +- phy-supply: see phy-bindings.txt in this directory + +Example: + pcie_phy: pcie-phy@ff644000 { + #phy-cells = <0>; + compatible = "amlogic,axg-pcie-phy"; + reg = <0x0 0xff644000 0x0 0x2000>; + resets = <&reset RESET_PCIE_PHY>; + reset-names = "phy"; + };