| Message ID | 20180823000904.25845-1-sjitindarsingh@gmail.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | KVM: PPC: Book3S HV: Set fault_dsisr on H_INST_STORAGE interrupts | expand |
diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c index ee4a8854985e..c5d29adec19a 100644 --- a/arch/powerpc/kvm/book3s_hv.c +++ b/arch/powerpc/kvm/book3s_hv.c @@ -1190,7 +1190,8 @@ static int kvmppc_handle_exit_hv(struct kvm_run *run, struct kvm_vcpu *vcpu, break; case BOOK3S_INTERRUPT_H_INST_STORAGE: vcpu->arch.fault_dar = kvmppc_get_pc(vcpu); - vcpu->arch.fault_dsisr = 0; + vcpu->arch.fault_dsisr = kvmppc_get_msr(vcpu) & + DSISR_SRR1_MATCH_64S; r = RESUME_PAGE_FAULT; break; /*
When a page fault is handled the bits in fault_dsisr are used to determine the cause of the fault. In the H_DATA_STORAGE interrupt case these bits come from the HDSISR register and are stored in fault_dsisr on vm exit. However for a H_INST_STORAGE interrupt fault_dsisr is set to zero. Currently we handle the page fault anyway, even if fault_dsisr is set to zero. However it means we can never update the RC bits of a pte on an instruction fault since the corresponding bit to indicate this is needed will never be set. On a H_INST_STORAGE interrupt the fault bits are in HSRR1 which is stored in the guest_msr on vm exit. So to correct this we mask the appropriate bits from the guest_msr and set it in fault_dsisr. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> --- arch/powerpc/kvm/book3s_hv.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)