From patchwork Tue May 17 22:32:36 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Filippov X-Patchwork-Id: 96060 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 3D8F1B6EED for ; Wed, 18 May 2011 08:35:27 +1000 (EST) Received: from localhost ([::1]:46601 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QMSrM-00007S-9k for incoming@patchwork.ozlabs.org; Tue, 17 May 2011 18:35:24 -0400 Received: from eggs.gnu.org ([140.186.70.92]:50561) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QMSpk-0006Jp-Lg for qemu-devel@nongnu.org; Tue, 17 May 2011 18:33:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QMSpj-0000P8-ME for qemu-devel@nongnu.org; Tue, 17 May 2011 18:33:44 -0400 Received: from mail-ey0-f173.google.com ([209.85.215.173]:53774) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QMSpj-0000MT-H5 for qemu-devel@nongnu.org; Tue, 17 May 2011 18:33:43 -0400 Received: by mail-ey0-f173.google.com with SMTP id 6so338540eyb.4 for ; Tue, 17 May 2011 15:33:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=JZXa+cYQQq1MDKxsyWVIRXvAiT30V30tbFmSeCEsEwA=; b=h1VUDzQevfNCfkGPGgMmWiqceSSe3f+k3P8Dw53ftM2W7WdLrtrpciyM/97AlcKxBz Ip765qYvWJJpGPpokdJk3zHkiafXr9AV9fEiwRWhx0ZFtPoqB2zJb0hC2zq8/CH5EEwe vUwurg9VqCOV9SoSiKIcMasJo9ZvNzSQdUDYI= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=rFeOEQqaRyAeVlikQBnSxV6fqPnbawcW3A8GS9PNrkerVZ8mlUYA4d/PSE6faDunlv PvgQQm4OqkHZQx5Y75tB3iu1uOhjJarGbdgRLpWmQXZFHiWJbxybE/yWBBid19uWs7tT /0hZKKXp5Plw+rSI+Q8bBg9Hf8/RLAg9QW25g= Received: by 10.213.102.212 with SMTP id h20mr774901ebo.128.1305671623037; Tue, 17 May 2011 15:33:43 -0700 (PDT) Received: from octofox.metropolis ([188.134.19.124]) by mx.google.com with ESMTPS id y20sm697782eeh.2.2011.05.17.15.33.40 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 17 May 2011 15:33:42 -0700 (PDT) Received: by octofox.metropolis (sSMTP sendmail emulation); Wed, 18 May 2011 02:33:39 +0400 From: Max Filippov To: qemu-devel@nongnu.org Date: Wed, 18 May 2011 02:32:36 +0400 Message-Id: <1305671572-5899-11-git-send-email-jcmvbkbc@gmail.com> X-Mailer: git-send-email 1.7.3.4 In-Reply-To: <1305671572-5899-1-git-send-email-jcmvbkbc@gmail.com> References: <1305671572-5899-1-git-send-email-jcmvbkbc@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 209.85.215.173 Cc: Max Filippov Subject: [Qemu-devel] [PATCH 10/26] target-xtensa: implement RST3 group X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org - access to Special Registers (wsr, rsr); - access to User Registers (wur, rur); - misc. operations option (value clamp, sign extension, min, max); - conditional moves. Signed-off-by: Max Filippov --- RFC -> PATCH changes: - optimize SEXT from bits 7 and 15; --- target-xtensa/translate.c | 161 +++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 161 insertions(+), 0 deletions(-) diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index 2fcd36d..b8e7813 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -165,6 +165,40 @@ static void gen_brcondi(DisasContext *dc, TCGCond cond, tcg_temp_free(tmp); } +static void gen_rsr(DisasContext *dc, TCGv_i32 d, uint32_t sr) +{ + static void (* const rsr_handler[256])(DisasContext *dc, + TCGv_i32 d, uint32_t sr) = { + }; + + if (sregnames[sr]) { + if (rsr_handler[sr]) { + rsr_handler[sr](dc, d, sr); + } else { + tcg_gen_mov_i32(d, cpu_SR[sr]); + } + } else { + qemu_log("RSR %d not implemented, ", sr); + } +} + +static void gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 s) +{ + static void (* const wsr_handler[256])(DisasContext *dc, + uint32_t sr, TCGv_i32 v) = { + }; + + if (sregnames[sr]) { + if (wsr_handler[sr]) { + wsr_handler[sr](dc, sr, s); + } else { + tcg_gen_mov_i32(cpu_SR[sr], s); + } + } else { + qemu_log("WSR %d not implemented, ", sr); + } +} + static void disas_xtensa_insn(DisasContext *dc) { #define HAS_OPTION(opt) do { \ @@ -413,6 +447,133 @@ static void disas_xtensa_insn(DisasContext *dc) break; case 3: /*RST3*/ + switch (_OP2) { + case 0: /*RSR*/ + gen_rsr(dc, cpu_R[RRR_T], RSR_SR); + break; + + case 1: /*WSR*/ + gen_wsr(dc, RSR_SR, cpu_R[RRR_T]); + break; + + case 2: /*SEXTu*/ + HAS_OPTION(XTENSA_OPTION_MISC_OP); + { + int shift = 24 - RRR_T; + + if (shift == 24) { + tcg_gen_ext8s_i32(cpu_R[RRR_R], cpu_R[RRR_S]); + } else if (shift == 16) { + tcg_gen_ext16s_i32(cpu_R[RRR_R], cpu_R[RRR_S]); + } else { + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_shli_i32(tmp, cpu_R[RRR_S], shift); + tcg_gen_sari_i32(cpu_R[RRR_R], tmp, shift); + tcg_temp_free(tmp); + } + } + break; + + case 3: /*CLAMPSu*/ + HAS_OPTION(XTENSA_OPTION_MISC_OP); + { + TCGv_i32 tmp1 = tcg_temp_new_i32(); + TCGv_i32 tmp2 = tcg_temp_new_i32(); + int label = gen_new_label(); + + tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 24 - RRR_T); + tcg_gen_xor_i32(tmp2, tmp1, cpu_R[RRR_S]); + tcg_gen_andi_i32(tmp2, tmp2, 0xffffffff << (RRR_T + 7)); + tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]); + tcg_gen_brcondi_i32(TCG_COND_EQ, tmp2, 0, label); + + tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 31); + tcg_gen_xori_i32(cpu_R[RRR_R], tmp1, + 0xffffffff >> (25 - RRR_T)); + + gen_set_label(label); + + tcg_temp_free(tmp1); + tcg_temp_free(tmp2); + } + break; + + case 4: /*MINu*/ + case 5: /*MAXu*/ + case 6: /*MINUu*/ + case 7: /*MAXUu*/ + HAS_OPTION(XTENSA_OPTION_MISC_OP); + { + static const TCGCond cond[] = { + TCG_COND_LE, + TCG_COND_GE, + TCG_COND_LEU, + TCG_COND_GEU + }; + int label = gen_new_label(); + + if (RRR_R != RRR_T) { + tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]); + tcg_gen_brcond_i32(cond[_OP2 - 4], + cpu_R[RRR_S], cpu_R[RRR_T], label); + tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_T]); + } else { + tcg_gen_brcond_i32(cond[_OP2 - 4], + cpu_R[RRR_T], cpu_R[RRR_S], label); + tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]); + } + gen_set_label(label); + } + break; + + case 8: /*MOVEQZ*/ + case 9: /*MOVNEZ*/ + case 10: /*MOVLTZ*/ + case 11: /*MOVGEZ*/ + { + static const TCGCond cond[] = { + TCG_COND_NE, + TCG_COND_EQ, + TCG_COND_GE, + TCG_COND_LT + }; + int label = gen_new_label(); + tcg_gen_brcondi_i32(cond[_OP2 - 8], cpu_R[RRR_T], 0, label); + tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]); + gen_set_label(label); + } + break; + + case 12: /*MOVFp*/ + HAS_OPTION(XTENSA_OPTION_BOOLEAN); + break; + + case 13: /*MOVTp*/ + HAS_OPTION(XTENSA_OPTION_BOOLEAN); + break; + + case 14: /*RUR*/ + { + int st = (RRR_S << 4) + RRR_T; + if (uregnames[st]) { + tcg_gen_mov_i32(cpu_R[RRR_R], cpu_UR[st]); + } else { + qemu_log("RUR %d not implemented, ", st); + } + } + break; + + case 15: /*WUR*/ + { + if (uregnames[RSR_SR]) { + tcg_gen_mov_i32(cpu_UR[RSR_SR], cpu_R[RRR_T]); + } else { + qemu_log("WUR %d not implemented, ", RSR_SR); + } + } + break; + + } break; case 4: /*EXTUI*/