| Message ID | 1534550915-18230-5-git-send-email-vnkgutta@codeaurora.org |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | Add EDAC driver for QCOM SoCs | expand |
On Fri, Aug 17, 2018 at 05:08:35PM -0700, Venkata Narendra Kumar Gutta wrote: > Add reg-names and interrupts for LLCC documentation and the usage > examples. llcc broadcast base is added in addition to llcc base, > which is used for llcc broadcast writes. Typo in the subject. This binding just landed recently and it's already being updated? Sigh. Bindings should be complete from the start. Technically, you can't add new required properties. > > Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org> > --- > Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt | 15 ++++++++++++++- > 1 file changed, 14 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt > index 5e85749..b4b1c86 100644 > --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt > +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt > @@ -18,9 +18,22 @@ Properties: > Value Type: <prop-encoded-array> > Definition: Start address and the the size of the register region. > > +- reg-names: > + Usage: required > + Value Type: <stringlist> > + Definition: Register region names. Must be "llcc_base", "llcc_bcast_base". reg needs to be updated that there are 2 entries. > + > +- interrupts: > + Usage: required > + Definition: The interrupt is associated with the llcc edac device. > + It's used for llcc cache single and double bit error detection > + and reporting. > + > Example: > > cache-controller@1100000 { > compatible = "qcom,sdm845-llcc"; > - reg = <0x1100000 0x250000>; > + reg = <0x1100000 0x200000>, <0x1300000 0x50000> ; > + reg-names = "llcc_base", "llcc_bcast_base"; > + interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; > }; > -- > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, > a Linux Foundation Collaborative Project >
On 2018-08-20 12:53, Rob Herring wrote: > On Fri, Aug 17, 2018 at 05:08:35PM -0700, Venkata Narendra Kumar Gutta > wrote: >> Add reg-names and interrupts for LLCC documentation and the usage >> examples. llcc broadcast base is added in addition to llcc base, >> which is used for llcc broadcast writes. > > Typo in the subject. > > This binding just landed recently and it's already being updated? Sigh. > Bindings should be complete from the start. Technically, you can't add > new required properties. Sure, I'll correct the typo. llcc broadcast base was being computed from the number of banks which was incorrect, so we have to add this property. And the interrupt is needed for EDAC functionality. > >> >> Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org> >> --- >> Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt | 15 >> ++++++++++++++- >> 1 file changed, 14 insertions(+), 1 deletion(-) >> >> diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt >> b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt >> index 5e85749..b4b1c86 100644 >> --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt >> +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt >> @@ -18,9 +18,22 @@ Properties: >> Value Type: <prop-encoded-array> >> Definition: Start address and the the size of the register region. >> >> +- reg-names: >> + Usage: required >> + Value Type: <stringlist> >> + Definition: Register region names. Must be "llcc_base", >> "llcc_bcast_base". > > reg needs to be updated that there are 2 entries. Ok, I'll update this in the next version. > >> + >> +- interrupts: >> + Usage: required >> + Definition: The interrupt is associated with the llcc edac device. >> + It's used for llcc cache single and double bit error detection >> + and reporting. >> + >> Example: >> >> cache-controller@1100000 { >> compatible = "qcom,sdm845-llcc"; >> - reg = <0x1100000 0x250000>; >> + reg = <0x1100000 0x200000>, <0x1300000 0x50000> ; >> + reg-names = "llcc_base", "llcc_bcast_base"; >> + interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; >> }; >> -- >> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora >> Forum, >> a Linux Foundation Collaborative Project >>
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt index 5e85749..b4b1c86 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt @@ -18,9 +18,22 @@ Properties: Value Type: <prop-encoded-array> Definition: Start address and the the size of the register region. +- reg-names: + Usage: required + Value Type: <stringlist> + Definition: Register region names. Must be "llcc_base", "llcc_bcast_base". + +- interrupts: + Usage: required + Definition: The interrupt is associated with the llcc edac device. + It's used for llcc cache single and double bit error detection + and reporting. + Example: cache-controller@1100000 { compatible = "qcom,sdm845-llcc"; - reg = <0x1100000 0x250000>; + reg = <0x1100000 0x200000>, <0x1300000 0x50000> ; + reg-names = "llcc_base", "llcc_bcast_base"; + interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; };
Add reg-names and interrupts for LLCC documentation and the usage examples. llcc broadcast base is added in addition to llcc base, which is used for llcc broadcast writes. Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org> --- Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-)