diff mbox series

[PULL,43/45] target/arm: Fix typo in do_sat_addsub_64

Message ID	20180814181815.23348-44-peter.maydell@linaro.org
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: Peter Maydell <peter.maydell@linaro.org> To: qemu-devel@nongnu.org Date: Tue, 14 Aug 2018 19:18:13 +0100 Message-Id: <20180814181815.23348-44-peter.maydell@linaro.org> In-Reply-To: <20180814181815.23348-1-peter.maydell@linaro.org> References: <20180814181815.23348-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PULL 43/45] target/arm: Fix typo in do_sat_addsub_64 Precedence: list Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>
Series	[PULL,01/45] target/arm: Forbid unprivileged mode for M Baseline \| expand [PULL,01/45] target/arm: Forbid unprivileged mode for M Baseline [PULL,02/45] nvic: Handle ARMv6-M SCS reserved registers [PULL,03/45] arm: Add ARMv6-M programmer's model support [PULL,04/45] nvic: Change NVIC to support ARMv6-M [PULL,05/45] accel/tcg: Pass read access type through to io_readx() [PULL,06/45] accel/tcg: Handle get_page_addr_code() returning -1 in hashtable lookups [PULL,07/45] accel/tcg: Handle get_page_addr_code() returning -1 in tb_check_watchpoint() [PULL,08/45] accel/tcg: tb_gen_code(): Create single-insn TB for execution from non-RAM [PULL,09/45] accel/tcg: Return -1 for execution from MMIO regions in get_page_addr_code() [PULL,10/45] target/arm: Allow execution from small regions [PULL,11/45] accel/tcg: Check whether TLB entry is RAM consistently with how we set it up [PULL,12/45] intc/arm_gic: Refactor operations on the distributor [PULL,13/45] intc/arm_gic: Implement GICD_ISACTIVERn and GICD_ICACTIVERn registers [PULL,14/45] intc/arm_gic: Remove some dead code and put some functions static [PULL,15/45] vmstate.h: Provide VMSTATE_UINT16_SUB_ARRAY [PULL,16/45] intc/arm_gic: Add the virtualization extensions to the GIC state [PULL,17/45] intc/arm_gic: Add virtual interface register definitions [PULL,18/45] intc/arm_gic: Add virtualization extensions helper macros and functions [PULL,19/45] intc/arm_gic: Refactor secure/ns access check in the CPU interface [PULL,20/45] intc/arm_gic: Add virtualization enabled IRQ helper functions [PULL,21/45] intc/arm_gic: Implement virtualization extensions in gic_(activate_irq\|drop_prio) [PULL,22/45] intc/arm_gic: Implement virtualization extensions in gic_acknowledge_irq [PULL,23/45] intc/arm_gic: Implement virtualization extensions in gic_(deactivate\|complete_irq) [PULL,24/45] intc/arm_gic: Implement virtualization extensions in gic_cpu_(read\|write) [PULL,25/45] intc/arm_gic: Wire the vCPU interface [PULL,26/45] intc/arm_gic: Implement the virtual interface registers [PULL,27/45] intc/arm_gic: Implement gic_update_virt() function [PULL,28/45] intc/arm_gic: Implement maintenance interrupt generation [PULL,29/45] intc/arm_gic: Improve traces [PULL,30/45] xlnx-zynqmp: Improve GIC wiring and MMIO mapping [PULL,31/45] arm/virt: Add support for GICv2 virtualization extensions [PULL,32/45] arm: Fix return code of arm_load_elf [PULL,33/45] target/arm: Mask virtual interrupts if HCR_EL2.TGE is set [PULL,34/45] target/arm: Honour HCR_EL2.TGE and MDCR_EL2.TDE in debug register access checks [PULL,35/45] target/arm: Honour HCR_EL2.TGE when raising synchronous exceptions [PULL,36/45] target/arm: Provide accessor functions for HCR_EL2.{IMO, FMO, AMO} [PULL,37/45] target/arm: Treat SCTLR_EL1.M as if it were zero when HCR_EL2.TGE is set [PULL,38/45] target/arm: Improve exception-taken logging [PULL,39/45] target/arm: Initialize exc_secure correctly in do_v7m_exception_exit() [PULL,40/45] target/arm: Restore M-profile CONTROL.SPSEL before any tailchaining [PULL,41/45] target/arm: Implement tailchaining for M profile cores [PULL,42/45] target/arm: Fix sign of sve_cmpeq_ppzw/sve_cmpne_ppzw [PULL,43/45] target/arm: Fix typo in do_sat_addsub_64 [PULL,44/45] target/arm: Reorganize SVE WHILE [PULL,45/45] target/arm: Fix typo in helper_sve_movz_d

Commit Message

Peter Maydell Aug. 14, 2018, 6:18 p.m. UTC

From: Richard Henderson <richard.henderson@linaro.org>

Used the wrong temporary in the computation of subtractive overflow.

Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Message-id: 20180801123111.3595-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-sve.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff mbox series

Patch

diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 374051cd20a..9dd4c38bab7 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -1625,7 +1625,7 @@  static void do_sat_addsub_64(TCGv_i64 reg, TCGv_i64 val, bool u, bool d)
             /* Detect signed overflow for subtraction.  */
             tcg_gen_xor_i64(t0, reg, val);
             tcg_gen_sub_i64(t1, reg, val);
-            tcg_gen_xor_i64(reg, reg, t0);
+            tcg_gen_xor_i64(reg, reg, t1);
             tcg_gen_and_i64(t0, t0, reg);
 
             /* Bound the result.  */