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[U-Boot,2/5] ARM: dts: socfpga: Add missing UART resets

Message ID 20180813185402.11197-2-marex@denx.de
State Accepted
Commit f5775e69cc201da6998dd992a93c1696e087d39a
Delegated to: Marek Vasut
Headers show
Series [U-Boot,1/5] ARM: dts: socfpga: Flag reset manager on A10 as pre-reloc | expand

Commit Message

Marek Vasut Aug. 13, 2018, 6:53 p.m. UTC 
The UART0 and UART1 resets are missing from DT, so the reset manager
cannot control them. Add the missing DT reset entries.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
---
 arch/arm/dts/socfpga_arria10.dtsi | 2 ++
 1 file changed, 2 insertions(+)
diff mbox series

Patch

diff --git a/arch/arm/dts/socfpga_arria10.dtsi b/arch/arm/dts/socfpga_arria10.dtsi
index 51b31dc2b5..aafcfe9ce4 100644
--- a/arch/arm/dts/socfpga_arria10.dtsi
+++ b/arch/arm/dts/socfpga_arria10.dtsi
@@ -797,6 +797,7 @@ 
 			reg-shift = <2>;
 			reg-io-width = <4>;
 			clocks = <&l4_sp_clk>;
+			resets = <&rst UART0_RESET>;
 			status = "disabled";
 		};
 
@@ -807,6 +808,7 @@ 
 			reg-shift = <2>;
 			reg-io-width = <4>;
 			clocks = <&l4_sp_clk>;
+			resets = <&rst UART1_RESET>;
 			status = "disabled";
 		};