@@ -17777,6 +17777,64 @@ static void gen_pool32axf_4_nanomips_insn(DisasContext *ctx, uint32_t opc,
tcg_temp_free(t0);
}
+static void gen_pool32axf_7_nanomips_insn(DisasContext *ctx, uint32_t opc,
+ int rt, int rs, int rd)
+{
+ TCGv t0;
+ TCGv rs_t;
+
+ if (rt == 0) {
+ /* Treat as NOP. */
+ return;
+ }
+
+ t0 = tcg_temp_new();
+ rs_t = tcg_temp_new();
+
+ gen_load_gpr(rs_t, rs);
+
+ switch (opc) {
+ case NM_SHRA_R_QB:
+ check_dspr2(ctx);
+ tcg_gen_movi_tl(t0, rd >> 2);
+ switch (extract32(ctx->opcode, 12, 1)) {
+ case 0:
+ /* NM_SHRA_QB */
+ gen_helper_shra_qb(cpu_gpr[rt], t0, rs_t);
+ break;
+ case 1:
+ /* NM_SHRA_R_QB */
+ gen_helper_shra_r_qb(cpu_gpr[rt], t0, rs_t);
+ break;
+ }
+ break;
+ case NM_SHRL_PH:
+ check_dspr2(ctx);
+ tcg_gen_movi_tl(t0, rd >> 1);
+ gen_helper_shrl_ph(cpu_gpr[rt], t0, rs_t);
+ break;
+ case NM_REPL_QB:
+ check_dsp(ctx);
+ {
+ int16_t imm;
+ target_long result;
+ imm = extract32(ctx->opcode, 13, 8);
+ result = (uint32_t)imm << 24 |
+ (uint32_t)imm << 16 |
+ (uint32_t)imm << 8 |
+ (uint32_t)imm;
+ result = (int32_t)result;
+ tcg_gen_movi_tl(cpu_gpr[rt], result);
+ }
+ break;
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+ tcg_temp_free(t0);
+ tcg_temp_free(rs_t);
+}
+
static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
{
@@ -17872,6 +17930,10 @@ static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
}
break;
case NM_POOL32AXF_7:
+ {
+ int32_t op1 = extract32(ctx->opcode, 9, 3);
+ gen_pool32axf_7_nanomips_insn(ctx, op1, rt, rs, rd);
+ }
break;
default:
generate_exception_end(ctx, EXCP_RI);