| Message ID | BANLkTimVJAJL=2Jxe+qDMKPtS8CLagYhBA@mail.gmail.com |
|---|---|
| State | New |
| Headers | show |
On Mon, May 16, 2011 at 12:50 PM, TeLeMan <geleman@gmail.com> wrote: > If pic_irq is greater than 7, the irq level is always 0 on 32bits. > > Signed-off-by: TeLeMan <geleman@gmail.com> > --- > hw/piix_pci.c | 2 +- > 1 files changed, 1 insertions(+), 1 deletions(-) Thanks, applied to the trivial-patches tree: http://repo.or.cz/w/qemu/stefanha.git/shortlog/refs/heads/trivial-patches Your patch is line-wrapped. I have manually applied it, please make sure future submissions are not line-wrapped. GMail's web interface always line wraps, you must use their SMTP server directly (e.g. with git-send-email(1)). Stefan
On Mon, May 16, 2011 at 07:50:55PM +0800, TeLeMan wrote: > If pic_irq is greater than 7, the irq level is always 0 on 32bits. > > Signed-off-by: TeLeMan <geleman@gmail.com> Good catch Acked-by: Michael S. Tsirkin <mst@redhat.com> > --- > hw/piix_pci.c | 2 +- > 1 files changed, 1 insertions(+), 1 deletions(-) > > diff --git a/hw/piix_pci.c b/hw/piix_pci.c > index 7f1c4cc..85a320e 100644 > --- a/hw/piix_pci.c > +++ b/hw/piix_pci.c > @@ -312,7 +312,7 @@ static void piix3_set_irq_pic(PIIX3State *piix3, > int pic_irq) > { > qemu_set_irq(piix3->pic[pic_irq], > !!(piix3->pic_levels & > - (((1UL << PIIX_NUM_PIRQS) - 1) << > + (((1ULL << PIIX_NUM_PIRQS) - 1) << > (pic_irq * PIIX_NUM_PIRQS)))); > } > > -- > 1.7.3.1.msysgit.0 > -- > SUN OF A BEACH
Am 22.05.2011 21:06, schrieb Michael S. Tsirkin: > On Mon, May 16, 2011 at 07:50:55PM +0800, TeLeMan wrote: >> If pic_irq is greater than 7, the irq level is always 0 on 32bits. >> >> Signed-off-by: TeLeMan <geleman@gmail.com> > > > Good catch > > Acked-by: Michael S. Tsirkin <mst@redhat.com> > The patch fixes the regression in Linux networking with 32 bit hosts. Tested with w32 and linux 32 bit hosts. Tested-by: Stefan Weil <weil@mail.berlios.de>
Thank you. Acked-by: Isaku Yamahata <yamahata@valinux.co.jp> On Mon, May 16, 2011 at 07:50:55PM +0800, TeLeMan wrote: > If pic_irq is greater than 7, the irq level is always 0 on 32bits. > > Signed-off-by: TeLeMan <geleman@gmail.com> > --- > hw/piix_pci.c | 2 +- > 1 files changed, 1 insertions(+), 1 deletions(-) > > diff --git a/hw/piix_pci.c b/hw/piix_pci.c > index 7f1c4cc..85a320e 100644 > --- a/hw/piix_pci.c > +++ b/hw/piix_pci.c > @@ -312,7 +312,7 @@ static void piix3_set_irq_pic(PIIX3State *piix3, > int pic_irq) > { > qemu_set_irq(piix3->pic[pic_irq], > !!(piix3->pic_levels & > - (((1UL << PIIX_NUM_PIRQS) - 1) << > + (((1ULL << PIIX_NUM_PIRQS) - 1) << > (pic_irq * PIIX_NUM_PIRQS)))); > } > > -- > 1.7.3.1.msysgit.0 > -- > SUN OF A BEACH >
diff --git a/hw/piix_pci.c b/hw/piix_pci.c index 7f1c4cc..85a320e 100644 --- a/hw/piix_pci.c +++ b/hw/piix_pci.c @@ -312,7 +312,7 @@ static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq) { qemu_set_irq(piix3->pic[pic_irq], !!(piix3->pic_levels & - (((1UL << PIIX_NUM_PIRQS) - 1) << + (((1ULL << PIIX_NUM_PIRQS) - 1) << (pic_irq * PIIX_NUM_PIRQS)))); }
If pic_irq is greater than 7, the irq level is always 0 on 32bits. Signed-off-by: TeLeMan <geleman@gmail.com> --- hw/piix_pci.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)