| Message ID | 20180813145755.16566-1-marc.zyngier@arm.com |
|---|---|
| State | New |
| Headers | show |
On Mon, Aug 13, 2018 at 03:57:41PM +0100, Marc Zyngier wrote: > From: Dongjiu Geng <gengdongjiu@huawei.com> > > For the arm64 RAS Extension, user space can inject a virtual-SError > with specified ESR. So user space needs to know whether KVM support > to inject such SError, this interface adds this query for this capability. > > KVM will check whether system support RAS Extension, if supported, KVM > returns true to user space, otherwise returns false. > > Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com> > Reviewed-by: James Morse <james.morse@arm.com> > [expanded documentation wording] > Signed-off-by: James Morse <james.morse@arm.com> > Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> > --- > Documentation/virtual/kvm/api.txt | 26 ++++++++++++++++++++++++++ > arch/arm64/kvm/reset.c | 3 +++ > include/uapi/linux/kvm.h | 1 + > 3 files changed, 30 insertions(+) > > diff --git a/Documentation/virtual/kvm/api.txt b/Documentation/virtual/kvm/api.txt > index 284d36e72f28..dbbb95d5798a 100644 > --- a/Documentation/virtual/kvm/api.txt > +++ b/Documentation/virtual/kvm/api.txt > @@ -907,6 +907,18 @@ SError is pending, the architecture's 'Multiple SError interrupts' rules should > be followed. (2.5.3 of DDI0587.a "ARM Reliability, Availability, and > Serviceability (RAS) Specification"). > > +SError exceptions always have an ESR value. Some CPUs have the ability to > +specify what the virtual SError's ESR value should be. These systems will > +advertise KVM_CAP_ARM_SET_SERROR_ESR. In this case exception.has_esr will > +always have a non-zero value when read, and the agent making an SError pending > +should specify the ISS field in the lower 24 bits of exception.serror_esr. If > +the system supports KVM_CAP_ARM_SET_SERROR_ESR, but user-space sets the events > +with exception.has_esr as zero, KVM will choose an ESR. > + > +Specifying exception.has_esr on a system that does not support it will return > +-EINVAL. Setting anything other than the lower 24bits of exception.serror_esr > +will return -EINVAL. > + > struct kvm_vcpu_events { > struct { > __u8 serror_pending; > @@ -4664,3 +4676,17 @@ This capability indicates that KVM supports paravirtualized Hyper-V TLB Flush > hypercalls: > HvFlushVirtualAddressSpace, HvFlushVirtualAddressSpaceEx, > HvFlushVirtualAddressList, HvFlushVirtualAddressListEx. > + > +8.19 KVM_CAP_ARM_SET_SERROR_ESR > + > +Architectures: arm, arm64 > + > +This capability indicates that userspace can specify (via the > +KVM_SET_VCPU_EVENTS ioctl) the syndrome value reported to the guest when it > +takes a virtual SError interrupt exception. > +If KVM advertises this capability, userspace can only specify the ISS field for > +the ESR syndrome. Other parts of the ESR, such as the EC are generated by the > +CPU when the exception is taken. If this virtual SError is taken to EL1 using > +AArch64, this value will be reported in the ISS field of ESR_ELx. > + > +See KVM_CAP_VCPU_EVENTS for more details. > diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c > index a3db01a28062..067c6ba969bd 100644 > --- a/arch/arm64/kvm/reset.c > +++ b/arch/arm64/kvm/reset.c > @@ -77,6 +77,9 @@ int kvm_arch_dev_ioctl_check_extension(struct kvm *kvm, long ext) > case KVM_CAP_ARM_PMU_V3: > r = kvm_arm_support_pmu_v3(); > break; > + case KVM_CAP_ARM_INJECT_SERROR_ESR: > + r = cpus_have_const_cap(ARM64_HAS_RAS_EXTN); > + break; > case KVM_CAP_SET_GUEST_DEBUG: > case KVM_CAP_VCPU_ATTRIBUTES: > case KVM_CAP_VCPU_EVENTS: > diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h > index b6270a3b38e9..a7d9bc4e4068 100644 > --- a/include/uapi/linux/kvm.h > +++ b/include/uapi/linux/kvm.h > @@ -949,6 +949,7 @@ struct kvm_ppc_resize_hpt { > #define KVM_CAP_GET_MSR_FEATURES 153 > #define KVM_CAP_HYPERV_EVENTFD 154 > #define KVM_CAP_HYPERV_TLBFLUSH 155 > +#define KVM_CAP_ARM_INJECT_SERROR_ESR 156 > > #ifdef KVM_CAP_IRQ_ROUTING > > -- > 2.18.0 > Hi All, I was just skimming over this patch and see that the documentation refers to KVM_CAP_ARM_SET_SERROR_ESR, but the code implements KVM_CAP_ARM_INJECT_SERROR_ESR. One or other needs a change. I suppose at this point the documentation would be easiest. Thanks, drew
On 15/08/18 13:13, Andrew Jones wrote: > On Mon, Aug 13, 2018 at 03:57:41PM +0100, Marc Zyngier wrote: >> From: Dongjiu Geng <gengdongjiu@huawei.com> >> >> For the arm64 RAS Extension, user space can inject a virtual-SError >> with specified ESR. So user space needs to know whether KVM support >> to inject such SError, this interface adds this query for this capability. >> >> KVM will check whether system support RAS Extension, if supported, KVM >> returns true to user space, otherwise returns false. >> >> Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com> >> Reviewed-by: James Morse <james.morse@arm.com> >> [expanded documentation wording] >> Signed-off-by: James Morse <james.morse@arm.com> >> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> >> --- >> Documentation/virtual/kvm/api.txt | 26 ++++++++++++++++++++++++++ >> arch/arm64/kvm/reset.c | 3 +++ >> include/uapi/linux/kvm.h | 1 + >> 3 files changed, 30 insertions(+) >> >> diff --git a/Documentation/virtual/kvm/api.txt b/Documentation/virtual/kvm/api.txt >> index 284d36e72f28..dbbb95d5798a 100644 >> --- a/Documentation/virtual/kvm/api.txt >> +++ b/Documentation/virtual/kvm/api.txt >> @@ -907,6 +907,18 @@ SError is pending, the architecture's 'Multiple SError interrupts' rules should >> be followed. (2.5.3 of DDI0587.a "ARM Reliability, Availability, and >> Serviceability (RAS) Specification"). >> >> +SError exceptions always have an ESR value. Some CPUs have the ability to >> +specify what the virtual SError's ESR value should be. These systems will >> +advertise KVM_CAP_ARM_SET_SERROR_ESR. In this case exception.has_esr will >> +always have a non-zero value when read, and the agent making an SError pending >> +should specify the ISS field in the lower 24 bits of exception.serror_esr. If >> +the system supports KVM_CAP_ARM_SET_SERROR_ESR, but user-space sets the events >> +with exception.has_esr as zero, KVM will choose an ESR. >> + >> +Specifying exception.has_esr on a system that does not support it will return >> +-EINVAL. Setting anything other than the lower 24bits of exception.serror_esr >> +will return -EINVAL. >> + >> struct kvm_vcpu_events { >> struct { >> __u8 serror_pending; >> @@ -4664,3 +4676,17 @@ This capability indicates that KVM supports paravirtualized Hyper-V TLB Flush >> hypercalls: >> HvFlushVirtualAddressSpace, HvFlushVirtualAddressSpaceEx, >> HvFlushVirtualAddressList, HvFlushVirtualAddressListEx. >> + >> +8.19 KVM_CAP_ARM_SET_SERROR_ESR >> + >> +Architectures: arm, arm64 >> + >> +This capability indicates that userspace can specify (via the >> +KVM_SET_VCPU_EVENTS ioctl) the syndrome value reported to the guest when it >> +takes a virtual SError interrupt exception. >> +If KVM advertises this capability, userspace can only specify the ISS field for >> +the ESR syndrome. Other parts of the ESR, such as the EC are generated by the >> +CPU when the exception is taken. If this virtual SError is taken to EL1 using >> +AArch64, this value will be reported in the ISS field of ESR_ELx. >> + >> +See KVM_CAP_VCPU_EVENTS for more details. >> diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c >> index a3db01a28062..067c6ba969bd 100644 >> --- a/arch/arm64/kvm/reset.c >> +++ b/arch/arm64/kvm/reset.c >> @@ -77,6 +77,9 @@ int kvm_arch_dev_ioctl_check_extension(struct kvm *kvm, long ext) >> case KVM_CAP_ARM_PMU_V3: >> r = kvm_arm_support_pmu_v3(); >> break; >> + case KVM_CAP_ARM_INJECT_SERROR_ESR: >> + r = cpus_have_const_cap(ARM64_HAS_RAS_EXTN); >> + break; >> case KVM_CAP_SET_GUEST_DEBUG: >> case KVM_CAP_VCPU_ATTRIBUTES: >> case KVM_CAP_VCPU_EVENTS: >> diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h >> index b6270a3b38e9..a7d9bc4e4068 100644 >> --- a/include/uapi/linux/kvm.h >> +++ b/include/uapi/linux/kvm.h >> @@ -949,6 +949,7 @@ struct kvm_ppc_resize_hpt { >> #define KVM_CAP_GET_MSR_FEATURES 153 >> #define KVM_CAP_HYPERV_EVENTFD 154 >> #define KVM_CAP_HYPERV_TLBFLUSH 155 >> +#define KVM_CAP_ARM_INJECT_SERROR_ESR 156 >> >> #ifdef KVM_CAP_IRQ_ROUTING >> >> -- >> 2.18.0 >> > > Hi All, > > I was just skimming over this patch and see that the documentation refers > to KVM_CAP_ARM_SET_SERROR_ESR, but the code implements > KVM_CAP_ARM_INJECT_SERROR_ESR. One or other needs a change. I suppose at > this point the documentation would be easiest. Oops. Don't know how we missed that. I'll queue another patch on top and send another pull request after -rc1 (I have another nit patch already on my plate). Thanks, M.
On 13/08/2018 16:57, Marc Zyngier wrote:
> git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm.git tags/kvmarm-for-v4.19
Pulled, thanks.
Paolo
Paolo, Radim, This is the bulk of the KVM/arm changes for 4.19. On the menu, the usual bulk of vgic changes (this time with group0 interrupt support), some cache management optimizations for recent versions of the architecture, some more RAS stuff and the usual collection of fixes. Please pull, M. The following changes since commit 1e4b044d22517cae7047c99038abb444423243ca: Linux 4.18-rc4 (2018-07-08 16:34:02 -0700) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm.git tags/kvmarm-for-v4.19 for you to fetch changes up to 976d34e2dab10ece5ea8fe7090b7692913f89084: KVM: arm/arm64: Skip updating PTE entry if no change (2018-08-13 15:32:01 +0100) ---------------------------------------------------------------- KVM/arm updates for 4.19 - Support for Group0 interrupts in guests - Cache management optimizations for ARMv8.4 systems - Userspace interface for RAS, allowing error retrival and injection - Fault path optimization - Emulated physical timer fixes - Random cleanups ---------------------------------------------------------------- Christoffer Dall (13): KVM: arm/arm64: Fix vgic init race KVM: arm/arm64: vgic: Define GICD_IIDR fields for GICv2 and GIv3 KVM: arm/arm64: vgic: Keep track of implementation revision KVM: arm/arm64: vgic: GICv2 IGROUPR should read as zero KVM: arm/arm64: vgic: Add group field to struct irq KVM: arm/arm64: vgic: Signal IRQs using their configured group KVM: arm/arm64: vgic: Permit uaccess writes to return errors KVM: arm/arm64: vgic: Return error on incompatible uaccess GICD_IIDR writes KVM: arm/arm64: vgic: Allow configuration of interrupt groups KVM: arm/arm64: vgic: Let userspace opt-in to writable v2 IGROUPR KVM: arm/arm64: vgic: Update documentation of the GIC devices wrt IIDR KVM: arm/arm64: Fix potential loss of ptimer interrupts KVM: arm/arm64: Fix lost IRQs from emulated physcial timer when blocked Dongjiu Geng (2): arm/arm64: KVM: Add KVM_GET/SET_VCPU_EVENTS arm64: KVM: export the capability to set guest SError syndrome Gustavo A. R. Silva (1): KVM: arm: Use true and false for boolean values James Morse (2): KVM: arm64: Share the parts of get/set events useful to 32bit KVM: arm: Add 32bit get/set events support Jia He (2): KVM: arm/arm64: vgic: Move DEBUG_SPINLOCK_BUG_ON to vgic.h KVM: arm/arm64: vgic: Do not use spin_lock_irqsave/restore with irq disabled Kees Cook (1): KVM: arm64: vgic-its: Remove VLA usage Marc Zyngier (13): arm64: KVM: Add support for Stage-2 control of memory types and cacheability arm64: KVM: Handle Set/Way CMOs as NOPs if FWB is present arm64: KVM: Avoid marking pages as XN in Stage-2 if CTR_EL0.DIC is set KVM: arm/arm64: Consolidate page-table accessors KVM: arm/arm64: Stop using the kernel's {pmd,pud,pgd}_populate helpers KVM: arm/arm64: Remove unnecessary CMOs when creating HYP page tables KVM: arm/arm64: Enable adaptative WFE trapping KVM: arm/arm64: vgic-debug: Show LPI status arm64: KVM: Cleanup tpidr_el2 init on non-VHE KVM: arm64: Remove non-existent AArch32 ICC_SGI1R encoding KVM: arm/arm64: vgic-v3: Add core support for Group0 SGIs KVM: arm64: vgic-v3: Add support for ICC_SGI0R_EL1 and ICC_ASGI1R_EL1 accesses KVM: arm: vgic-v3: Add support for ICC_SGI0R and ICC_ASGI1R accesses Mark Rutland (1): KVM: arm/arm64: vgic: Fix possible spectre-v1 write in vgic_mmio_write_apr() Punit Agrawal (2): KVM: arm/arm64: Skip updating PMD entry if no change KVM: arm/arm64: Skip updating PTE entry if no change Documentation/virtual/kvm/api.txt | 80 +++++++++++++++++++-- Documentation/virtual/kvm/devices/arm-vgic-v3.txt | 8 +++ Documentation/virtual/kvm/devices/arm-vgic.txt | 15 ++-- arch/arm/include/asm/kvm_emulate.h | 12 +++- arch/arm/include/asm/kvm_host.h | 5 ++ arch/arm/include/asm/kvm_mmu.h | 14 +--- arch/arm/include/uapi/asm/kvm.h | 13 ++++ arch/arm/kvm/coproc.c | 25 ++++++- arch/arm/kvm/guest.c | 23 ++++++ arch/arm64/include/asm/cpucaps.h | 3 +- arch/arm64/include/asm/kvm_arm.h | 1 + arch/arm64/include/asm/kvm_emulate.h | 17 +++++ arch/arm64/include/asm/kvm_host.h | 28 ++++---- arch/arm64/include/asm/kvm_mmu.h | 35 ++++++--- arch/arm64/include/asm/memory.h | 7 ++ arch/arm64/include/asm/pgtable-prot.h | 24 ++++++- arch/arm64/include/asm/sysreg.h | 3 + arch/arm64/include/uapi/asm/kvm.h | 13 ++++ arch/arm64/kernel/cpufeature.c | 20 ++++++ arch/arm64/kvm/guest.c | 33 +++++++++ arch/arm64/kvm/hyp-init.S | 6 +- arch/arm64/kvm/hyp/sysreg-sr.c | 5 -- arch/arm64/kvm/inject_fault.c | 6 +- arch/arm64/kvm/reset.c | 4 ++ arch/arm64/kvm/sys_regs.c | 54 ++++++++++++-- include/kvm/arm_vgic.h | 9 ++- include/linux/irqchip/arm-gic-v3.h | 10 +++ include/linux/irqchip/arm-gic.h | 11 +++ include/uapi/linux/kvm.h | 1 + virt/kvm/arm/arch_timer.c | 15 ++-- virt/kvm/arm/arm.c | 51 +++++++++++++ virt/kvm/arm/mmu.c | 87 ++++++++++++++++++----- virt/kvm/arm/vgic/vgic-debug.c | 50 +++++++++---- virt/kvm/arm/vgic/vgic-init.c | 24 ++++++- virt/kvm/arm/vgic/vgic-its.c | 27 ++++--- virt/kvm/arm/vgic/vgic-mmio-v2.c | 66 +++++++++++++++-- virt/kvm/arm/vgic/vgic-mmio-v3.c | 72 ++++++++++++++----- virt/kvm/arm/vgic/vgic-mmio.c | 56 +++++++++++++-- virt/kvm/arm/vgic/vgic-mmio.h | 25 ++++--- virt/kvm/arm/vgic/vgic-v2.c | 10 ++- virt/kvm/arm/vgic/vgic-v3.c | 13 ++-- virt/kvm/arm/vgic/vgic.c | 19 ++--- virt/kvm/arm/vgic/vgic.h | 7 ++ 43 files changed, 834 insertions(+), 173 deletions(-)