[1/6] target/arm: Adjust FPCR_MASK for FZ16

Message ID 20180810193129.1556-2-richard.henderson@linaro.org
State New
Headers show
Series
  • target/arm: More sve-ish fixes
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Commit Message

Richard Henderson Aug. 10, 2018, 7:31 p.m.
When support for FZ16 was added, we failed to include the bit
within FPCR_MASK, which means that it could never be set.
Continue to zero FZ16 when ARMv8.2-FP16 is not enabled.

Fixes: d81ce0ef2c4
Cc: qemu-stable@nongnu.org (3.0.1)
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/cpu.h    | 2 +-
 target/arm/helper.c | 5 +++++
 2 files changed, 6 insertions(+), 1 deletion(-)

Comments

Laurent Desnogues Aug. 11, 2018, 4:22 p.m. | #1
On Fri, Aug 10, 2018 at 9:31 PM, Richard Henderson
<richard.henderson@linaro.org> wrote:
> When support for FZ16 was added, we failed to include the bit
> within FPCR_MASK, which means that it could never be set.
> Continue to zero FZ16 when ARMv8.2-FP16 is not enabled.
>
> Fixes: d81ce0ef2c4
> Cc: qemu-stable@nongnu.org (3.0.1)
> Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>

Laurent

> ---
>  target/arm/cpu.h    | 2 +-
>  target/arm/helper.c | 5 +++++
>  2 files changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index 33d06f2340..0176716a70 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -1279,7 +1279,7 @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val);
>   * we store the underlying state in fpscr and just mask on read/write.
>   */
>  #define FPSR_MASK 0xf800009f
> -#define FPCR_MASK 0x07f79f00
> +#define FPCR_MASK 0x07ff9f00
>
>  #define FPCR_FZ16   (1 << 19)   /* ARMv8.2+, FP16 flush-to-zero */
>  #define FPCR_FZ     (1 << 24)   /* Flush-to-zero enable bit */
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 64ff71b722..452d5e182a 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -11351,6 +11351,11 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
>      int i;
>      uint32_t changed;
>
> +    /* When ARMv8.2-FP16 is not supported, FZ16 is RES0.  */
> +    if (!arm_feature(env, ARM_FEATURE_V8_FP16)) {
> +        val &= ~FPCR_FZ16;
> +    }
> +
>      changed = env->vfp.xregs[ARM_VFP_FPSCR];
>      env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
>      env->vfp.vec_len = (val >> 16) & 7;
> --
> 2.17.1
>

Patch

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 33d06f2340..0176716a70 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1279,7 +1279,7 @@  void vfp_set_fpscr(CPUARMState *env, uint32_t val);
  * we store the underlying state in fpscr and just mask on read/write.
  */
 #define FPSR_MASK 0xf800009f
-#define FPCR_MASK 0x07f79f00
+#define FPCR_MASK 0x07ff9f00
 
 #define FPCR_FZ16   (1 << 19)   /* ARMv8.2+, FP16 flush-to-zero */
 #define FPCR_FZ     (1 << 24)   /* Flush-to-zero enable bit */
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 64ff71b722..452d5e182a 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -11351,6 +11351,11 @@  void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
     int i;
     uint32_t changed;
 
+    /* When ARMv8.2-FP16 is not supported, FZ16 is RES0.  */
+    if (!arm_feature(env, ARM_FEATURE_V8_FP16)) {
+        val &= ~FPCR_FZ16;
+    }
+
     changed = env->vfp.xregs[ARM_VFP_FPSCR];
     env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
     env->vfp.vec_len = (val >> 16) & 7;