[v2,2/3] target/riscv: optimize indirect branches

Message ID 20180810173941.5301-3-cota@braap.org
State New
Headers show
Series
  • Untitled series #60322
Related show

Commit Message

Emilio G. Cota Aug. 10, 2018, 5:39 p.m.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Emilio G. Cota <cota@braap.org>
---
 target/riscv/translate.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Patch

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index ec2988b4f6..66a80ca772 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -548,7 +548,7 @@  static void gen_jalr(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
         if (rd != 0) {
             tcg_gen_movi_tl(cpu_gpr[rd], ctx->pc_succ_insn);
         }
-        tcg_gen_exit_tb(NULL, 0);
+        tcg_gen_lookup_and_goto_ptr();
 
         if (misaligned) {
             gen_set_label(misaligned);