[U-Boot,v1,1/4] ARM: dts: stm32mp1: Add usb gadget support for stm32mp157c-ev1 board

Message ID 1533913935-27058-2-git-send-email-patrice.chotard@st.com
State Accepted
Commit 8e9c94d7663510cbf31cb1d1a30b73f220ccb171
Delegated to: Tom Rini
Headers show
Series
  • Add USB EHCI and gadget support for STM32MP1
Related show

Commit Message

Patrice CHOTARD Aug. 10, 2018, 3:12 p.m.
Add DT nodes to enable DWC2 gadget support

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---

 arch/arm/dts/stm32mp157-pinctrl.dtsi     |  6 ++++++
 arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi |  5 +++++
 arch/arm/dts/stm32mp157c-ev1.dts         |  8 +++++++
 arch/arm/dts/stm32mp157c.dtsi            | 36 ++++++++++++++++++++++++++++++++
 4 files changed, 55 insertions(+)

Comments

Tom Rini Sept. 26, 2018, 12:42 p.m. | #1
On Fri, Aug 10, 2018 at 05:12:11PM +0200, Patrice Chotard wrote:

> Add DT nodes to enable DWC2 gadget support
> 
> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>

Applied to u-boot/master, thanks!

Patch

diff --git a/arch/arm/dts/stm32mp157-pinctrl.dtsi b/arch/arm/dts/stm32mp157-pinctrl.dtsi
index c69c397964af..85da5926551c 100644
--- a/arch/arm/dts/stm32mp157-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp157-pinctrl.dtsi
@@ -321,6 +321,12 @@ 
 					bias-disable;
 				};
 			};
+
+			usbotg_hs_pins_a: usbotg_hs-0 {
+				pins {
+					pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */
+				};
+			};
 		};
 
 		pinctrl_z: pin-controller-z@54004000 {
diff --git a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi
index 2f4de3a066c0..30b173478c6c 100644
--- a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi
@@ -25,6 +25,10 @@ 
 	regulator-always-on;
 };
 
+&usbotg_hs {
+	g-tx-fifo-size = <576>;
+};
+
 /* SPL part **************************************/
 &qspi {
 	u-boot,dm-spl;
@@ -60,3 +64,4 @@ 
 &flash0 {
 	u-boot,dm-spl;
 };
+
diff --git a/arch/arm/dts/stm32mp157c-ev1.dts b/arch/arm/dts/stm32mp157c-ev1.dts
index d6934f74e076..e2128af93fe5 100644
--- a/arch/arm/dts/stm32mp157c-ev1.dts
+++ b/arch/arm/dts/stm32mp157c-ev1.dts
@@ -96,6 +96,14 @@ 
 	};
 };
 
+&usbotg_hs {
+	pinctrl-names = "default";
+	pinctrl-0 = <&usbotg_hs_pins_a>;
+	phys = <&usbphyc_port1 0>;
+	phy-names = "usb2-phy";
+	status = "okay";
+};
+
 &usbphyc {
 	status = "okay";
 };
diff --git a/arch/arm/dts/stm32mp157c.dtsi b/arch/arm/dts/stm32mp157c.dtsi
index 8df9f09dc6c3..44190394e7af 100644
--- a/arch/arm/dts/stm32mp157c.dtsi
+++ b/arch/arm/dts/stm32mp157c.dtsi
@@ -106,6 +106,26 @@ 
 		};
 	};
 
+	pm_domain {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "st,stm32mp157c-pd";
+
+		pd_core_ret: core-ret-power-domain@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+			#power-domain-cells = <0>;
+			label = "CORE-RETENTION";
+
+			pd_core: core-power-domain@2 {
+				reg = <2>;
+				#power-domain-cells = <0>;
+				label = "CORE";
+			};
+		};
+	};
+
 	soc {
 		compatible = "simple-bus";
 		#address-cells = <1>;
@@ -622,6 +642,22 @@ 
 			status = "disabled";
 		};
 
+		usbotg_hs: usb-otg@49000000 {
+			compatible = "st,stm32mp1-hsotg", "snps,dwc2";
+			reg = <0x49000000 0x10000>;
+			clocks = <&rcc USBO_K>;
+			clock-names = "otg";
+			resets = <&rcc USBO_R>;
+			reset-names = "dwc2";
+			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+			g-rx-fifo-size = <256>;
+			g-np-tx-fifo-size = <32>;
+			g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
+			dr_mode = "otg";
+			power-domains = <&pd_core>;
+			status = "disabled";
+		};
+
 		rcc: rcc@50000000 {
 			compatible = "st,stm32mp1-rcc", "syscon";
 			reg = <0x50000000 0x1000>;