[U-Boot,5/6] x86: coreboot: Add default TSC frequency in the device tree

Message ID 1533893978-12838-5-git-send-email-bmeng.cn@gmail.com
State Accepted
Commit 864915561b3273a4f8894804146d6739e8e49ab2
Delegated to: Bin Meng
Headers show
Series
  • [U-Boot,1/6] x86: coreboot: Add generic coreboot payload support
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Commit Message

Bin Meng Aug. 10, 2018, 9:39 a.m.
It was observed sometimes U-Boot as the coreboot payload fails to
boot on QEMU. This is because TSC calibration fails with no valid
frequency. This adds default TSC frequency in the device tree.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 arch/x86/dts/coreboot.dts | 4 ++++
 1 file changed, 4 insertions(+)

Comments

Christian Gmeiner Aug. 14, 2018, 6:45 a.m. | #1
Am Fr., 10. Aug. 2018 um 11:39 Uhr schrieb Bin Meng <bmeng.cn@gmail.com>:
>
> It was observed sometimes U-Boot as the coreboot payload fails to
> boot on QEMU. This is because TSC calibration fails with no valid
> frequency. This adds default TSC frequency in the device tree.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>

> ---
>
>  arch/x86/dts/coreboot.dts | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/arch/x86/dts/coreboot.dts b/arch/x86/dts/coreboot.dts
> index a94f781..e212f3d 100644
> --- a/arch/x86/dts/coreboot.dts
> +++ b/arch/x86/dts/coreboot.dts
> @@ -30,6 +30,10 @@
>                 stdout-path = "/serial";
>         };
>
> +       tsc-timer {
> +               clock-frequency = <1000000000>;
> +       };
> +
>         pci {
>                 compatible = "pci-x86";
>                 u-boot,dm-pre-reloc;
> --
> 2.7.4
>
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> U-Boot mailing list
> U-Boot@lists.denx.de
> https://lists.denx.de/listinfo/u-boot
Bin Meng Aug. 20, 2018, 5:57 a.m. | #2
On Tue, Aug 14, 2018 at 2:45 PM, Christian Gmeiner
<christian.gmeiner@gmail.com> wrote:
> Am Fr., 10. Aug. 2018 um 11:39 Uhr schrieb Bin Meng <bmeng.cn@gmail.com>:
>>
>> It was observed sometimes U-Boot as the coreboot payload fails to
>> boot on QEMU. This is because TSC calibration fails with no valid
>> frequency. This adds default TSC frequency in the device tree.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>
> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
>

applied to u-boot-x86, thanks!

Patch

diff --git a/arch/x86/dts/coreboot.dts b/arch/x86/dts/coreboot.dts
index a94f781..e212f3d 100644
--- a/arch/x86/dts/coreboot.dts
+++ b/arch/x86/dts/coreboot.dts
@@ -30,6 +30,10 @@ 
 		stdout-path = "/serial";
 	};
 
+	tsc-timer {
+		clock-frequency = <1000000000>;
+	};
+
 	pci {
 		compatible = "pci-x86";
 		u-boot,dm-pre-reloc;