[U-Boot,v2] spi: Add SPI driver for MT76xx SoCs

Message ID 20180810065654.9316-1-sr@denx.de
State Superseded
Delegated to: Jagannadha Sutradharudu Teki
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Series
  • [U-Boot,v2] spi: Add SPI driver for MT76xx SoCs
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Commit Message

Stefan Roese Aug. 10, 2018, 6:56 a.m.
This patch adds the SPI driver for the MediaTek MT7688 SoC (and
derivates). Its been tested on the LinkIt Smart 7688 and the Gardena
Smart Gateway with and SPI NOR on CS0 and on the Gardena Smart
Gateway additionally with an SPI NAND on CS1.

Note that the SPI controller only supports a max transfer size of 32
bytes. This driver implementes a workaround to enable bigger xfer
sizes to speed up the transfer especially for the SPI NAND support.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Jagan Teki <jagan@openedev.com>
---
v2:
- Add some macros instead of hardcoded numbers
- Move compatible DT struct down in the file

 drivers/spi/Kconfig      |   8 +
 drivers/spi/Makefile     |   1 +
 drivers/spi/mt76xx_spi.c | 319 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 328 insertions(+)
 create mode 100644 drivers/spi/mt76xx_spi.c

Comments

Jagan Teki Aug. 10, 2018, 7:25 a.m. | #1
On Fri, Aug 10, 2018 at 12:26 PM, Stefan Roese <sr@denx.de> wrote:
> This patch adds the SPI driver for the MediaTek MT7688 SoC (and
> derivates). Its been tested on the LinkIt Smart 7688 and the Gardena
> Smart Gateway with and SPI NOR on CS0 and on the Gardena Smart
> Gateway additionally with an SPI NAND on CS1.
>
> Note that the SPI controller only supports a max transfer size of 32
> bytes. This driver implementes a workaround to enable bigger xfer
> sizes to speed up the transfer especially for the SPI NAND support.
>
> Signed-off-by: Stefan Roese <sr@denx.de>
> Cc: Jagan Teki <jagan@openedev.com>
> ---
> v2:
> - Add some macros instead of hardcoded numbers
> - Move compatible DT struct down in the file

Reviewed-by: Jagan Teki <jagan@openedev.com>
Daniel Schwierzeck Aug. 11, 2018, 4:59 p.m. | #2
On 10.08.2018 08:56, Stefan Roese wrote:
> This patch adds the SPI driver for the MediaTek MT7688 SoC (and
> derivates). Its been tested on the LinkIt Smart 7688 and the Gardena
> Smart Gateway with and SPI NOR on CS0 and on the Gardena Smart
> Gateway additionally with an SPI NAND on CS1.
> 
> Note that the SPI controller only supports a max transfer size of 32
> bytes. This driver implementes a workaround to enable bigger xfer
> sizes to speed up the transfer especially for the SPI NAND support.
> 
> Signed-off-by: Stefan Roese <sr@denx.de>
> Cc: Jagan Teki <jagan@openedev.com>
> ---
> v2:
> - Add some macros instead of hardcoded numbers
> - Move compatible DT struct down in the file
> 
>  drivers/spi/Kconfig      |   8 +
>  drivers/spi/Makefile     |   1 +
>  drivers/spi/mt76xx_spi.c | 319 +++++++++++++++++++++++++++++++++++++++
>  3 files changed, 328 insertions(+)
>  create mode 100644 drivers/spi/mt76xx_spi.c
> 
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> index 9fbd26740d..6c4e50d3e9 100644
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -116,6 +116,14 @@ config ICH_SPI
>  	  access the SPI NOR flash on platforms embedding this Intel
>  	  ICH IP core.
>  
> +config MT76XX_SPI
> +	bool "MediaTek MT76XX SPI driver"
> +	depends on ARCH_MT7620
> +	help
> +	  Enable the MT76XX SPI driver. This driver can be used to access
> +	  the SPI NOR flash on platforms embedding these MediaTek
> +	  SPI cores.
> +
>  config MVEBU_A3700_SPI
>  	bool "Marvell Armada 3700 SPI driver"
>  	select CLK_ARMADA_3720
> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
> index bdb5b5a02f..3d13ba1b21 100644
> --- a/drivers/spi/Makefile
> +++ b/drivers/spi/Makefile
> @@ -33,6 +33,7 @@ obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
>  obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o
>  obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o
>  obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
> +obj-$(CONFIG_MT76XX_SPI) += mt76xx_spi.o
>  obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o
>  obj-$(CONFIG_MXC_SPI) += mxc_spi.o
>  obj-$(CONFIG_MXS_SPI) += mxs_spi.o
> diff --git a/drivers/spi/mt76xx_spi.c b/drivers/spi/mt76xx_spi.c
> new file mode 100644
> index 0000000000..f26b5341ce
> --- /dev/null
> +++ b/drivers/spi/mt76xx_spi.c
> @@ -0,0 +1,319 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2018 Stefan Roese <sr@denx.de>
> + *
> + * Derived from the Linux driver version drivers/spi/spi-mt7621.c
> + *   Copyright (C) 2011 Sergiy <piratfm@gmail.com>
> + *   Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
> + *   Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name>
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <spi.h>
> +#include <wait_bit.h>
> +#include <linux/io.h>
> +
> +#define SPI_MSG_SIZE_MAX	32	/* SPI message chunk size */
> +/* Enough for SPI NAND page read / write with page size 2048 bytes */
> +#define SPI_MSG_SIZE_OVERALL	(2048 + 16)
> +
> +#define MT7621_SPI_TRANS	0x00
> +#define MT7621_SPI_TRANS_START	BIT(8)
> +#define MT7621_SPI_TRANS_BUSY	BIT(16)
> +
> +#define MT7621_SPI_OPCODE	0x04
> +#define MT7621_SPI_DATA0	0x08
> +#define MT7621_SPI_DATA4	0x18
> +#define MT7621_SPI_MASTER	0x28
> +#define MT7621_SPI_MOREBUF	0x2c
> +#define MT7621_SPI_POLAR	0x38
> +
> +#define MT7621_LSB_FIRST	BIT(3)
> +#define MT7621_CPOL		BIT(4)
> +#define MT7621_CPHA		BIT(5)
> +
> +#define MASTER_MORE_BUFMODE	BIT(2)
> +#define MASTER_RS_CLK_SEL	GENMASK(27, 16)
> +#define MASTER_RS_CLK_SEL_SHIFT	16
> +#define MASTER_RS_SLAVE_SEL	GENMASK(31, 29)
> +
> +struct mt7621_spi {
> +	void __iomem *base;
> +	unsigned int sys_freq;
> +	u32 data[(SPI_MSG_SIZE_OVERALL / 4) + 1];
> +	int tx_len;
> +};
> +
> +static inline u32 mt7621_spi_read(struct mt7621_spi *rs, u32 reg)
> +{
> +	return ioread32(rs->base + reg);
> +}
> +
> +static inline void mt7621_spi_write(struct mt7621_spi *rs, u32 reg, u32 val)
> +{
> +	iowrite32(val, rs->base + reg);
> +}
> +
> +static void mt7621_spi_reset(struct mt7621_spi *rs, int duplex)
> +{
> +	u32 master = mt7621_spi_read(rs, MT7621_SPI_MASTER);
> +
> +	master |= MASTER_RS_SLAVE_SEL;	/* CS control */
> +	master |= MASTER_MORE_BUFMODE;	/* more_buf_mode */
> +
> +	mt7621_spi_write(rs, MT7621_SPI_MASTER, master);

if you omit the (actually unneeded) I/O wrappers, you could simplify
this with setbits_le32() (or setbits_32() for non-enforcing endianess)

> +}
> +
> +static void mt7621_spi_set_cs(struct mt7621_spi *rs, int cs, int enable)
> +{
> +	u32 val = 0;
> +
> +	debug("%s: cs#%d -> %s\n", __func__, cs, enable ? "enable" : "disable");
> +	if (enable)
> +		val = BIT(cs);
> +	mt7621_spi_write(rs, MT7621_SPI_POLAR, val);
> +}
> +
> +static int mt7621_spi_set_mode(struct udevice *bus, uint mode)
> +{
> +	struct mt7621_spi *rs = dev_get_priv(bus);
> +	u32 reg;
> +
> +	debug("%s: mode=0x%08x\n", __func__, mode);
> +	reg = mt7621_spi_read(rs, MT7621_SPI_MASTER);
> +
> +	reg &= ~MT7621_LSB_FIRST;
> +	if (mode & SPI_LSB_FIRST)
> +		reg |= MT7621_LSB_FIRST;
> +
> +	reg &= ~(MT7621_CPHA | MT7621_CPOL);
> +	switch (mode & (SPI_CPOL | SPI_CPHA)) {
> +	case SPI_MODE_0:
> +		break;
> +	case SPI_MODE_1:
> +		reg |= MT7621_CPHA;
> +		break;
> +	case SPI_MODE_2:
> +		reg |= MT7621_CPOL;
> +		break;
> +	case SPI_MODE_3:
> +		reg |= MT7621_CPOL | MT7621_CPHA;
> +		break;
> +	}
> +	mt7621_spi_write(rs, MT7621_SPI_MASTER, reg);
> +
> +	return 0;
> +}
> +
> +static int mt7621_spi_set_speed(struct udevice *bus, uint speed)
> +{
> +	struct mt7621_spi *rs = dev_get_priv(bus);
> +	u32 rate;
> +	u32 reg;
> +
> +	debug("%s: speed=%d\n", __func__, speed);
> +	rate = DIV_ROUND_UP(rs->sys_freq, speed);
> +	debug("rate:%u\n", rate);
> +
> +	if (rate > 4097)
> +		return -EINVAL;
> +
> +	if (rate < 2)
> +		rate = 2;
> +
> +	reg = mt7621_spi_read(rs, MT7621_SPI_MASTER);
> +	reg &= ~MASTER_RS_CLK_SEL;
> +	reg |= (rate - 2) << MASTER_RS_CLK_SEL_SHIFT;
> +	mt7621_spi_write(rs, MT7621_SPI_MASTER, reg);
> +
> +	return 0;
> +}
> +
> +static inline int mt7621_spi_wait_till_ready(struct mt7621_spi *rs)
> +{
> +	int ret;
> +
> +	ret =  wait_for_bit_le32(rs->base + MT7621_SPI_TRANS,
> +				 MT7621_SPI_TRANS_BUSY, 0, 10, 0);
> +	if (ret)
> +		pr_err("Timeout in %s!\n", __func__);
> +
> +	return ret;
> +}
> +
> +static int mt7621_spi_xfer(struct udevice *dev, unsigned int bitlen,
> +			   const void *dout, void *din, unsigned long flags)
> +{
> +	struct udevice *bus = dev->parent;
> +	struct mt7621_spi *rs = dev_get_priv(bus);
> +	const u8 *tx_buf = dout;
> +	u8 *ptr = (u8 *)dout;
> +	u8 *rx_buf = din;
> +	int total_size = bitlen >> 3;
> +	int chunk_size;
> +	int rx_len = 0;
> +	u32 data[(SPI_MSG_SIZE_MAX / 4) + 1] = { 0 };
> +	u32 val;
> +	int i;
> +
> +	debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__, dout, din,
> +	      total_size, flags);
> +
> +	/*
> +	 * This driver only supports half-duplex, so complain and bail out
> +	 * upon full-duplex messages
> +	 */
> +	if (dout && din) {
> +		printf("Only half-duplex SPI transfer supported\n");
> +		return -EIO;
> +	}
> +
> +	if (dout) {
> +		debug("TX-DATA: ");
> +		for (i = 0; i < total_size; i++)
> +			debug("%02x ", *ptr++);
> +		debug("\n");
> +	}
> +
> +	mt7621_spi_wait_till_ready(rs);
> +
> +	/*
> +	 * Set CS active upon start of SPI message. This message can
> +	 * be split upon multiple calls to this xfer function
> +	 */
> +	if (flags & SPI_XFER_BEGIN)
> +		mt7621_spi_set_cs(rs, spi_chip_select(dev), 1);
> +
> +	while (total_size > 0) {
> +		/* Don't exceed the max xfer size */
> +		chunk_size = min_t(int, total_size, SPI_MSG_SIZE_MAX);
> +
> +		/*
> +		 * We might have some TX data buffered from the last xfer
> +		 * message. Make sure, that this does not exceed the max
> +		 * xfer size
> +		 */
> +		if (rs->tx_len > 4)
> +			chunk_size -= rs->tx_len;
> +		if (din)
> +			rx_len = chunk_size;
> +
> +		if (tx_buf) {
> +			/* Check if this message does not exceed the buffer */
> +			if ((chunk_size + rs->tx_len) > SPI_MSG_SIZE_OVERALL) {
> +				printf("TX message size too big (%d)\n",
> +				       chunk_size + rs->tx_len);
> +				return -EMSGSIZE;
> +			}
> +
> +			/*
> +			 * Write all TX data into internal buffer to collect
> +			 * all TX messages into one buffer (might be split into
> +			 * multiple calls to this function)
> +			 */
> +			for (i = 0; i < chunk_size; i++, rs->tx_len++) {
> +				rs->data[rs->tx_len / 4] |=
> +					tx_buf[i] << (8 * (rs->tx_len & 3));
> +			}
> +		}
> +
> +		if (flags & SPI_XFER_END) {
> +			/* Write TX data into controller */
> +			if (rs->tx_len) {
> +				rs->data[0] = swab32(rs->data[0]);
> +				if (rs->tx_len < 4)
> +					rs->data[0] >>= (4 - rs->tx_len) * 8;
> +
> +				for (i = 0; i < rs->tx_len; i += 4) {
> +					mt7621_spi_write(rs,
> +							 MT7621_SPI_OPCODE + i,
> +							 rs->data[i / 4]);
> +				}
> +			}
> +
> +			/* Write length into controller */
> +			val = (min_t(int, rs->tx_len, 4) * 8) << 24;
> +			if (rs->tx_len > 4)
> +				val |= (rs->tx_len - 4) * 8;
> +			val |= (rx_len * 8) << 12;
> +			mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val);
> +
> +			/* Start the xfer */
> +			val = mt7621_spi_read(rs, MT7621_SPI_TRANS);
> +			val |= MT7621_SPI_TRANS_START;
> +			mt7621_spi_write(rs, MT7621_SPI_TRANS, val);
> +
> +			/* Wait until xfer is finished on bus */
> +			mt7621_spi_wait_till_ready(rs);
> +
> +			/* Reset TX length and TX buffer for next xfer */
> +			rs->tx_len = 0;
> +			memset(rs->data, 0, sizeof(rs->data));
> +		}
> +
> +		for (i = 0; i < rx_len; i += 4)
> +			data[i / 4] = mt7621_spi_read(rs, MT7621_SPI_DATA0 + i);
> +
> +		if (rx_len) {
> +			debug("RX-DATA: ");
> +			for (i = 0; i < rx_len; i++) {
> +				rx_buf[i] = data[i / 4] >> (8 * (i & 3));
> +				debug("%02x ", rx_buf[i]);
> +			}
> +			debug("\n");
> +		}
> +
> +		if (tx_buf)
> +			tx_buf += chunk_size;
> +		if (rx_buf)
> +			rx_buf += chunk_size;
> +		total_size -= chunk_size;
> +	}
> +
> +	/* Wait until xfer is finished on bus and de-assert CS */
> +	mt7621_spi_wait_till_ready(rs);
> +	if (flags & SPI_XFER_END)
> +		mt7621_spi_set_cs(rs, spi_chip_select(dev), 0);
> +
> +	return 0;
> +}
> +
> +static int mt76xx_spi_probe(struct udevice *dev)
> +{
> +	struct mt7621_spi *rs = dev_get_priv(dev);
> +
> +	rs->base = dev_remap_addr(dev);
> +	if (!rs->base)
> +		return -EINVAL;
> +
> +	rs->sys_freq = CONFIG_SYS_MIPS_TIMER_FREQ;

you should create a minimal clock driver based on the system controller
block. The SPI clock has a separate bit for clock gating, so at least
one driver has to take care of enabling that clock. Also using
CONFIG_SYS_MIPS_TIMER_FREQ is a bad choice because it is a hard-coded
value which is usually the CPU clock divided by two. But CPU clock and
SYS clock are derived from PLL clock and can be configured with
different dividers.

> +
> +	mt7621_spi_reset(rs, 0);
> +
> +	return 0;
> +}
> +
> +static const struct dm_spi_ops mt7621_spi_ops = {
> +	.set_mode = mt7621_spi_set_mode,
> +	.set_speed = mt7621_spi_set_speed,
> +	.xfer = mt7621_spi_xfer,
> +	/*
> +	 * cs_info is not needed, since we require all chip selects to be
> +	 * in the device tree explicitly
> +	 */
> +};
> +
> +static const struct udevice_id mt76xx_spi_ids[] = {
> +	{ .compatible = "ralink,mt7621-spi" },
> +	{ }
> +};
> +
> +U_BOOT_DRIVER(mt76xx_spi) = {
> +	.name = "mt76xx_spi",
> +	.id = UCLASS_SPI,
> +	.of_match = mt76xx_spi_ids,
> +	.ops = &mt7621_spi_ops,
> +	.priv_auto_alloc_size = sizeof(struct mt7621_spi),
> +	.probe = mt76xx_spi_probe,
> +};
>
Stefan Roese Aug. 15, 2018, 11:26 a.m. | #3
Hi Daniel,

On 11.08.2018 18:59, Daniel Schwierzeck wrote:
> On 10.08.2018 08:56, Stefan Roese wrote:
>> This patch adds the SPI driver for the MediaTek MT7688 SoC (and
>> derivates). Its been tested on the LinkIt Smart 7688 and the Gardena
>> Smart Gateway with and SPI NOR on CS0 and on the Gardena Smart
>> Gateway additionally with an SPI NAND on CS1.
>>
>> Note that the SPI controller only supports a max transfer size of 32
>> bytes. This driver implementes a workaround to enable bigger xfer
>> sizes to speed up the transfer especially for the SPI NAND support.
>>
>> Signed-off-by: Stefan Roese <sr@denx.de>
>> Cc: Jagan Teki <jagan@openedev.com>
>> ---
>> v2:
>> - Add some macros instead of hardcoded numbers
>> - Move compatible DT struct down in the file
>>
>>   drivers/spi/Kconfig      |   8 +
>>   drivers/spi/Makefile     |   1 +
>>   drivers/spi/mt76xx_spi.c | 319 +++++++++++++++++++++++++++++++++++++++
>>   3 files changed, 328 insertions(+)
>>   create mode 100644 drivers/spi/mt76xx_spi.c
>>
>> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
>> index 9fbd26740d..6c4e50d3e9 100644
>> --- a/drivers/spi/Kconfig
>> +++ b/drivers/spi/Kconfig
>> @@ -116,6 +116,14 @@ config ICH_SPI
>>   	  access the SPI NOR flash on platforms embedding this Intel
>>   	  ICH IP core.
>>   
>> +config MT76XX_SPI
>> +	bool "MediaTek MT76XX SPI driver"
>> +	depends on ARCH_MT7620
>> +	help
>> +	  Enable the MT76XX SPI driver. This driver can be used to access
>> +	  the SPI NOR flash on platforms embedding these MediaTek
>> +	  SPI cores.
>> +
>>   config MVEBU_A3700_SPI
>>   	bool "Marvell Armada 3700 SPI driver"
>>   	select CLK_ARMADA_3720
>> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
>> index bdb5b5a02f..3d13ba1b21 100644
>> --- a/drivers/spi/Makefile
>> +++ b/drivers/spi/Makefile
>> @@ -33,6 +33,7 @@ obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
>>   obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o
>>   obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o
>>   obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
>> +obj-$(CONFIG_MT76XX_SPI) += mt76xx_spi.o
>>   obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o
>>   obj-$(CONFIG_MXC_SPI) += mxc_spi.o
>>   obj-$(CONFIG_MXS_SPI) += mxs_spi.o
>> diff --git a/drivers/spi/mt76xx_spi.c b/drivers/spi/mt76xx_spi.c
>> new file mode 100644
>> index 0000000000..f26b5341ce
>> --- /dev/null
>> +++ b/drivers/spi/mt76xx_spi.c
>> @@ -0,0 +1,319 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * Copyright (C) 2018 Stefan Roese <sr@denx.de>
>> + *
>> + * Derived from the Linux driver version drivers/spi/spi-mt7621.c
>> + *   Copyright (C) 2011 Sergiy <piratfm@gmail.com>
>> + *   Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
>> + *   Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name>
>> + */
>> +
>> +#include <common.h>
>> +#include <dm.h>
>> +#include <spi.h>
>> +#include <wait_bit.h>
>> +#include <linux/io.h>
>> +
>> +#define SPI_MSG_SIZE_MAX	32	/* SPI message chunk size */
>> +/* Enough for SPI NAND page read / write with page size 2048 bytes */
>> +#define SPI_MSG_SIZE_OVERALL	(2048 + 16)
>> +
>> +#define MT7621_SPI_TRANS	0x00
>> +#define MT7621_SPI_TRANS_START	BIT(8)
>> +#define MT7621_SPI_TRANS_BUSY	BIT(16)
>> +
>> +#define MT7621_SPI_OPCODE	0x04
>> +#define MT7621_SPI_DATA0	0x08
>> +#define MT7621_SPI_DATA4	0x18
>> +#define MT7621_SPI_MASTER	0x28
>> +#define MT7621_SPI_MOREBUF	0x2c
>> +#define MT7621_SPI_POLAR	0x38
>> +
>> +#define MT7621_LSB_FIRST	BIT(3)
>> +#define MT7621_CPOL		BIT(4)
>> +#define MT7621_CPHA		BIT(5)
>> +
>> +#define MASTER_MORE_BUFMODE	BIT(2)
>> +#define MASTER_RS_CLK_SEL	GENMASK(27, 16)
>> +#define MASTER_RS_CLK_SEL_SHIFT	16
>> +#define MASTER_RS_SLAVE_SEL	GENMASK(31, 29)
>> +
>> +struct mt7621_spi {
>> +	void __iomem *base;
>> +	unsigned int sys_freq;
>> +	u32 data[(SPI_MSG_SIZE_OVERALL / 4) + 1];
>> +	int tx_len;
>> +};
>> +
>> +static inline u32 mt7621_spi_read(struct mt7621_spi *rs, u32 reg)
>> +{
>> +	return ioread32(rs->base + reg);
>> +}
>> +
>> +static inline void mt7621_spi_write(struct mt7621_spi *rs, u32 reg, u32 val)
>> +{
>> +	iowrite32(val, rs->base + reg);
>> +}
>> +
>> +static void mt7621_spi_reset(struct mt7621_spi *rs, int duplex)
>> +{
>> +	u32 master = mt7621_spi_read(rs, MT7621_SPI_MASTER);
>> +
>> +	master |= MASTER_RS_SLAVE_SEL;	/* CS control */
>> +	master |= MASTER_MORE_BUFMODE;	/* more_buf_mode */
>> +
>> +	mt7621_spi_write(rs, MT7621_SPI_MASTER, master);
> 
> if you omit the (actually unneeded) I/O wrappers, you could simplify
> this with setbits_le32() (or setbits_32() for non-enforcing endianess)

Yes, you are correct. All this is derived / copied from the Linux
driver. Even though the main xfer routine is pretty much different,
so it makes not much sense any more to stick with this IO wrappers
for code compatibility.

I could work on a new version of this driver, omitting these IO
wrappers, if this is preferred. Or I could do this in a follow-up
patch, once this one is in mainline (time is a bit short right now).

>> +}
>> +
>> +static void mt7621_spi_set_cs(struct mt7621_spi *rs, int cs, int enable)
>> +{
>> +	u32 val = 0;
>> +
>> +	debug("%s: cs#%d -> %s\n", __func__, cs, enable ? "enable" : "disable");
>> +	if (enable)
>> +		val = BIT(cs);
>> +	mt7621_spi_write(rs, MT7621_SPI_POLAR, val);
>> +}
>> +
>> +static int mt7621_spi_set_mode(struct udevice *bus, uint mode)
>> +{
>> +	struct mt7621_spi *rs = dev_get_priv(bus);
>> +	u32 reg;
>> +
>> +	debug("%s: mode=0x%08x\n", __func__, mode);
>> +	reg = mt7621_spi_read(rs, MT7621_SPI_MASTER);
>> +
>> +	reg &= ~MT7621_LSB_FIRST;
>> +	if (mode & SPI_LSB_FIRST)
>> +		reg |= MT7621_LSB_FIRST;
>> +
>> +	reg &= ~(MT7621_CPHA | MT7621_CPOL);
>> +	switch (mode & (SPI_CPOL | SPI_CPHA)) {
>> +	case SPI_MODE_0:
>> +		break;
>> +	case SPI_MODE_1:
>> +		reg |= MT7621_CPHA;
>> +		break;
>> +	case SPI_MODE_2:
>> +		reg |= MT7621_CPOL;
>> +		break;
>> +	case SPI_MODE_3:
>> +		reg |= MT7621_CPOL | MT7621_CPHA;
>> +		break;
>> +	}
>> +	mt7621_spi_write(rs, MT7621_SPI_MASTER, reg);
>> +
>> +	return 0;
>> +}
>> +
>> +static int mt7621_spi_set_speed(struct udevice *bus, uint speed)
>> +{
>> +	struct mt7621_spi *rs = dev_get_priv(bus);
>> +	u32 rate;
>> +	u32 reg;
>> +
>> +	debug("%s: speed=%d\n", __func__, speed);
>> +	rate = DIV_ROUND_UP(rs->sys_freq, speed);
>> +	debug("rate:%u\n", rate);
>> +
>> +	if (rate > 4097)
>> +		return -EINVAL;
>> +
>> +	if (rate < 2)
>> +		rate = 2;
>> +
>> +	reg = mt7621_spi_read(rs, MT7621_SPI_MASTER);
>> +	reg &= ~MASTER_RS_CLK_SEL;
>> +	reg |= (rate - 2) << MASTER_RS_CLK_SEL_SHIFT;
>> +	mt7621_spi_write(rs, MT7621_SPI_MASTER, reg);
>> +
>> +	return 0;
>> +}
>> +
>> +static inline int mt7621_spi_wait_till_ready(struct mt7621_spi *rs)
>> +{
>> +	int ret;
>> +
>> +	ret =  wait_for_bit_le32(rs->base + MT7621_SPI_TRANS,
>> +				 MT7621_SPI_TRANS_BUSY, 0, 10, 0);
>> +	if (ret)
>> +		pr_err("Timeout in %s!\n", __func__);
>> +
>> +	return ret;
>> +}
>> +
>> +static int mt7621_spi_xfer(struct udevice *dev, unsigned int bitlen,
>> +			   const void *dout, void *din, unsigned long flags)
>> +{
>> +	struct udevice *bus = dev->parent;
>> +	struct mt7621_spi *rs = dev_get_priv(bus);
>> +	const u8 *tx_buf = dout;
>> +	u8 *ptr = (u8 *)dout;
>> +	u8 *rx_buf = din;
>> +	int total_size = bitlen >> 3;
>> +	int chunk_size;
>> +	int rx_len = 0;
>> +	u32 data[(SPI_MSG_SIZE_MAX / 4) + 1] = { 0 };
>> +	u32 val;
>> +	int i;
>> +
>> +	debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__, dout, din,
>> +	      total_size, flags);
>> +
>> +	/*
>> +	 * This driver only supports half-duplex, so complain and bail out
>> +	 * upon full-duplex messages
>> +	 */
>> +	if (dout && din) {
>> +		printf("Only half-duplex SPI transfer supported\n");
>> +		return -EIO;
>> +	}
>> +
>> +	if (dout) {
>> +		debug("TX-DATA: ");
>> +		for (i = 0; i < total_size; i++)
>> +			debug("%02x ", *ptr++);
>> +		debug("\n");
>> +	}
>> +
>> +	mt7621_spi_wait_till_ready(rs);
>> +
>> +	/*
>> +	 * Set CS active upon start of SPI message. This message can
>> +	 * be split upon multiple calls to this xfer function
>> +	 */
>> +	if (flags & SPI_XFER_BEGIN)
>> +		mt7621_spi_set_cs(rs, spi_chip_select(dev), 1);
>> +
>> +	while (total_size > 0) {
>> +		/* Don't exceed the max xfer size */
>> +		chunk_size = min_t(int, total_size, SPI_MSG_SIZE_MAX);
>> +
>> +		/*
>> +		 * We might have some TX data buffered from the last xfer
>> +		 * message. Make sure, that this does not exceed the max
>> +		 * xfer size
>> +		 */
>> +		if (rs->tx_len > 4)
>> +			chunk_size -= rs->tx_len;
>> +		if (din)
>> +			rx_len = chunk_size;
>> +
>> +		if (tx_buf) {
>> +			/* Check if this message does not exceed the buffer */
>> +			if ((chunk_size + rs->tx_len) > SPI_MSG_SIZE_OVERALL) {
>> +				printf("TX message size too big (%d)\n",
>> +				       chunk_size + rs->tx_len);
>> +				return -EMSGSIZE;
>> +			}
>> +
>> +			/*
>> +			 * Write all TX data into internal buffer to collect
>> +			 * all TX messages into one buffer (might be split into
>> +			 * multiple calls to this function)
>> +			 */
>> +			for (i = 0; i < chunk_size; i++, rs->tx_len++) {
>> +				rs->data[rs->tx_len / 4] |=
>> +					tx_buf[i] << (8 * (rs->tx_len & 3));
>> +			}
>> +		}
>> +
>> +		if (flags & SPI_XFER_END) {
>> +			/* Write TX data into controller */
>> +			if (rs->tx_len) {
>> +				rs->data[0] = swab32(rs->data[0]);
>> +				if (rs->tx_len < 4)
>> +					rs->data[0] >>= (4 - rs->tx_len) * 8;
>> +
>> +				for (i = 0; i < rs->tx_len; i += 4) {
>> +					mt7621_spi_write(rs,
>> +							 MT7621_SPI_OPCODE + i,
>> +							 rs->data[i / 4]);
>> +				}
>> +			}
>> +
>> +			/* Write length into controller */
>> +			val = (min_t(int, rs->tx_len, 4) * 8) << 24;
>> +			if (rs->tx_len > 4)
>> +				val |= (rs->tx_len - 4) * 8;
>> +			val |= (rx_len * 8) << 12;
>> +			mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val);
>> +
>> +			/* Start the xfer */
>> +			val = mt7621_spi_read(rs, MT7621_SPI_TRANS);
>> +			val |= MT7621_SPI_TRANS_START;
>> +			mt7621_spi_write(rs, MT7621_SPI_TRANS, val);
>> +
>> +			/* Wait until xfer is finished on bus */
>> +			mt7621_spi_wait_till_ready(rs);
>> +
>> +			/* Reset TX length and TX buffer for next xfer */
>> +			rs->tx_len = 0;
>> +			memset(rs->data, 0, sizeof(rs->data));
>> +		}
>> +
>> +		for (i = 0; i < rx_len; i += 4)
>> +			data[i / 4] = mt7621_spi_read(rs, MT7621_SPI_DATA0 + i);
>> +
>> +		if (rx_len) {
>> +			debug("RX-DATA: ");
>> +			for (i = 0; i < rx_len; i++) {
>> +				rx_buf[i] = data[i / 4] >> (8 * (i & 3));
>> +				debug("%02x ", rx_buf[i]);
>> +			}
>> +			debug("\n");
>> +		}
>> +
>> +		if (tx_buf)
>> +			tx_buf += chunk_size;
>> +		if (rx_buf)
>> +			rx_buf += chunk_size;
>> +		total_size -= chunk_size;
>> +	}
>> +
>> +	/* Wait until xfer is finished on bus and de-assert CS */
>> +	mt7621_spi_wait_till_ready(rs);
>> +	if (flags & SPI_XFER_END)
>> +		mt7621_spi_set_cs(rs, spi_chip_select(dev), 0);
>> +
>> +	return 0;
>> +}
>> +
>> +static int mt76xx_spi_probe(struct udevice *dev)
>> +{
>> +	struct mt7621_spi *rs = dev_get_priv(dev);
>> +
>> +	rs->base = dev_remap_addr(dev);
>> +	if (!rs->base)
>> +		return -EINVAL;
>> +
>> +	rs->sys_freq = CONFIG_SYS_MIPS_TIMER_FREQ;
> 
> you should create a minimal clock driver based on the system controller
> block. The SPI clock has a separate bit for clock gating, so at least
> one driver has to take care of enabling that clock. Also using
> CONFIG_SYS_MIPS_TIMER_FREQ is a bad choice because it is a hard-coded
> value which is usually the CPU clock divided by two. But CPU clock and
> SYS clock are derived from PLL clock and can be configured with
> different dividers.

Yes, this all sounds like a good idea. Unfortunately this work is not
trivial, as (at least to my knowledge) no such clock driver exist
in Linux right now. Documentation for the MT7688 is also very "limited"
and the Linux DT has no clock nodes at all.

As time is very limited right now for such "improvements", would it
be acceptable to add such a minimal clock driver at a later time?

Thanks,
Stefan
Daniel Schwierzeck Aug. 15, 2018, 12:02 p.m. | #4
On 15.08.2018 13:26, Stefan Roese wrote:
> Hi Daniel,
> 
> On 11.08.2018 18:59, Daniel Schwierzeck wrote:
>> On 10.08.2018 08:56, Stefan Roese wrote:
>>> This patch adds the SPI driver for the MediaTek MT7688 SoC (and
>>> derivates). Its been tested on the LinkIt Smart 7688 and the Gardena
>>> Smart Gateway with and SPI NOR on CS0 and on the Gardena Smart
>>> Gateway additionally with an SPI NAND on CS1.
>>>
>>> Note that the SPI controller only supports a max transfer size of 32
>>> bytes. This driver implementes a workaround to enable bigger xfer
>>> sizes to speed up the transfer especially for the SPI NAND support.
>>>
>>> Signed-off-by: Stefan Roese <sr@denx.de>
>>> Cc: Jagan Teki <jagan@openedev.com>
>>> ---
>>> v2:
>>> - Add some macros instead of hardcoded numbers
>>> - Move compatible DT struct down in the file
>>>
>>>   drivers/spi/Kconfig      |   8 +
>>>   drivers/spi/Makefile     |   1 +
>>>   drivers/spi/mt76xx_spi.c | 319 +++++++++++++++++++++++++++++++++++++++
>>>   3 files changed, 328 insertions(+)
>>>   create mode 100644 drivers/spi/mt76xx_spi.c
>>>
>>> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
>>> index 9fbd26740d..6c4e50d3e9 100644
>>> --- a/drivers/spi/Kconfig
>>> +++ b/drivers/spi/Kconfig
>>> @@ -116,6 +116,14 @@ config ICH_SPI
>>>         access the SPI NOR flash on platforms embedding this Intel
>>>         ICH IP core.
>>>   +config MT76XX_SPI
>>> +    bool "MediaTek MT76XX SPI driver"
>>> +    depends on ARCH_MT7620
>>> +    help
>>> +      Enable the MT76XX SPI driver. This driver can be used to access
>>> +      the SPI NOR flash on platforms embedding these MediaTek
>>> +      SPI cores.
>>> +
>>>   config MVEBU_A3700_SPI
>>>       bool "Marvell Armada 3700 SPI driver"
>>>       select CLK_ARMADA_3720
>>> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
>>> index bdb5b5a02f..3d13ba1b21 100644
>>> --- a/drivers/spi/Makefile
>>> +++ b/drivers/spi/Makefile
>>> @@ -33,6 +33,7 @@ obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
>>>   obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o
>>>   obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o
>>>   obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
>>> +obj-$(CONFIG_MT76XX_SPI) += mt76xx_spi.o
>>>   obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o
>>>   obj-$(CONFIG_MXC_SPI) += mxc_spi.o
>>>   obj-$(CONFIG_MXS_SPI) += mxs_spi.o
>>> diff --git a/drivers/spi/mt76xx_spi.c b/drivers/spi/mt76xx_spi.c
>>> new file mode 100644
>>> index 0000000000..f26b5341ce
>>> --- /dev/null
>>> +++ b/drivers/spi/mt76xx_spi.c
>>> @@ -0,0 +1,319 @@
>>> +// SPDX-License-Identifier: GPL-2.0+
>>> +/*
>>> + * Copyright (C) 2018 Stefan Roese <sr@denx.de>
>>> + *
>>> + * Derived from the Linux driver version drivers/spi/spi-mt7621.c
>>> + *   Copyright (C) 2011 Sergiy <piratfm@gmail.com>
>>> + *   Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
>>> + *   Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name>
>>> + */
>>> +
>>> +#include <common.h>
>>> +#include <dm.h>
>>> +#include <spi.h>
>>> +#include <wait_bit.h>
>>> +#include <linux/io.h>
>>> +
>>> +#define SPI_MSG_SIZE_MAX    32    /* SPI message chunk size */
>>> +/* Enough for SPI NAND page read / write with page size 2048 bytes */
>>> +#define SPI_MSG_SIZE_OVERALL    (2048 + 16)
>>> +
>>> +#define MT7621_SPI_TRANS    0x00
>>> +#define MT7621_SPI_TRANS_START    BIT(8)
>>> +#define MT7621_SPI_TRANS_BUSY    BIT(16)
>>> +
>>> +#define MT7621_SPI_OPCODE    0x04
>>> +#define MT7621_SPI_DATA0    0x08
>>> +#define MT7621_SPI_DATA4    0x18
>>> +#define MT7621_SPI_MASTER    0x28
>>> +#define MT7621_SPI_MOREBUF    0x2c
>>> +#define MT7621_SPI_POLAR    0x38
>>> +
>>> +#define MT7621_LSB_FIRST    BIT(3)
>>> +#define MT7621_CPOL        BIT(4)
>>> +#define MT7621_CPHA        BIT(5)
>>> +
>>> +#define MASTER_MORE_BUFMODE    BIT(2)
>>> +#define MASTER_RS_CLK_SEL    GENMASK(27, 16)
>>> +#define MASTER_RS_CLK_SEL_SHIFT    16
>>> +#define MASTER_RS_SLAVE_SEL    GENMASK(31, 29)
>>> +
>>> +struct mt7621_spi {
>>> +    void __iomem *base;
>>> +    unsigned int sys_freq;
>>> +    u32 data[(SPI_MSG_SIZE_OVERALL / 4) + 1];
>>> +    int tx_len;
>>> +};
>>> +
>>> +static inline u32 mt7621_spi_read(struct mt7621_spi *rs, u32 reg)
>>> +{
>>> +    return ioread32(rs->base + reg);
>>> +}
>>> +
>>> +static inline void mt7621_spi_write(struct mt7621_spi *rs, u32 reg,
>>> u32 val)
>>> +{
>>> +    iowrite32(val, rs->base + reg);
>>> +}
>>> +
>>> +static void mt7621_spi_reset(struct mt7621_spi *rs, int duplex)
>>> +{
>>> +    u32 master = mt7621_spi_read(rs, MT7621_SPI_MASTER);
>>> +
>>> +    master |= MASTER_RS_SLAVE_SEL;    /* CS control */
>>> +    master |= MASTER_MORE_BUFMODE;    /* more_buf_mode */
>>> +
>>> +    mt7621_spi_write(rs, MT7621_SPI_MASTER, master);
>>
>> if you omit the (actually unneeded) I/O wrappers, you could simplify
>> this with setbits_le32() (or setbits_32() for non-enforcing endianess)
> 
> Yes, you are correct. All this is derived / copied from the Linux
> driver. Even though the main xfer routine is pretty much different,
> so it makes not much sense any more to stick with this IO wrappers
> for code compatibility.
> 
> I could work on a new version of this driver, omitting these IO
> wrappers, if this is preferred. Or I could do this in a follow-up
> patch, once this one is in mainline (time is a bit short right now).

follow-up patch would be ok, it was only meant as optional improvement.

But maybe the mt7621_ prefix could be replaced with mt76xx_ to be
consistent with the source file name?

> 
>>> +}
>>> +
>>> +static void mt7621_spi_set_cs(struct mt7621_spi *rs, int cs, int
>>> enable)
>>> +{
>>> +    u32 val = 0;
>>> +
>>> +    debug("%s: cs#%d -> %s\n", __func__, cs, enable ? "enable" :
>>> "disable");
>>> +    if (enable)
>>> +        val = BIT(cs);
>>> +    mt7621_spi_write(rs, MT7621_SPI_POLAR, val);
>>> +}
>>> +
>>> +static int mt7621_spi_set_mode(struct udevice *bus, uint mode)
>>> +{
>>> +    struct mt7621_spi *rs = dev_get_priv(bus);
>>> +    u32 reg;
>>> +
>>> +    debug("%s: mode=0x%08x\n", __func__, mode);
>>> +    reg = mt7621_spi_read(rs, MT7621_SPI_MASTER);
>>> +
>>> +    reg &= ~MT7621_LSB_FIRST;
>>> +    if (mode & SPI_LSB_FIRST)
>>> +        reg |= MT7621_LSB_FIRST;
>>> +
>>> +    reg &= ~(MT7621_CPHA | MT7621_CPOL);
>>> +    switch (mode & (SPI_CPOL | SPI_CPHA)) {
>>> +    case SPI_MODE_0:
>>> +        break;
>>> +    case SPI_MODE_1:
>>> +        reg |= MT7621_CPHA;
>>> +        break;
>>> +    case SPI_MODE_2:
>>> +        reg |= MT7621_CPOL;
>>> +        break;
>>> +    case SPI_MODE_3:
>>> +        reg |= MT7621_CPOL | MT7621_CPHA;
>>> +        break;
>>> +    }
>>> +    mt7621_spi_write(rs, MT7621_SPI_MASTER, reg);
>>> +
>>> +    return 0;
>>> +}
>>> +
>>> +static int mt7621_spi_set_speed(struct udevice *bus, uint speed)
>>> +{
>>> +    struct mt7621_spi *rs = dev_get_priv(bus);
>>> +    u32 rate;
>>> +    u32 reg;
>>> +
>>> +    debug("%s: speed=%d\n", __func__, speed);
>>> +    rate = DIV_ROUND_UP(rs->sys_freq, speed);
>>> +    debug("rate:%u\n", rate);
>>> +
>>> +    if (rate > 4097)
>>> +        return -EINVAL;
>>> +
>>> +    if (rate < 2)
>>> +        rate = 2;
>>> +
>>> +    reg = mt7621_spi_read(rs, MT7621_SPI_MASTER);
>>> +    reg &= ~MASTER_RS_CLK_SEL;
>>> +    reg |= (rate - 2) << MASTER_RS_CLK_SEL_SHIFT;
>>> +    mt7621_spi_write(rs, MT7621_SPI_MASTER, reg);
>>> +
>>> +    return 0;
>>> +}
>>> +
>>> +static inline int mt7621_spi_wait_till_ready(struct mt7621_spi *rs)
>>> +{
>>> +    int ret;
>>> +
>>> +    ret =  wait_for_bit_le32(rs->base + MT7621_SPI_TRANS,
>>> +                 MT7621_SPI_TRANS_BUSY, 0, 10, 0);
>>> +    if (ret)
>>> +        pr_err("Timeout in %s!\n", __func__);
>>> +
>>> +    return ret;
>>> +}
>>> +
>>> +static int mt7621_spi_xfer(struct udevice *dev, unsigned int bitlen,
>>> +               const void *dout, void *din, unsigned long flags)
>>> +{
>>> +    struct udevice *bus = dev->parent;
>>> +    struct mt7621_spi *rs = dev_get_priv(bus);
>>> +    const u8 *tx_buf = dout;
>>> +    u8 *ptr = (u8 *)dout;
>>> +    u8 *rx_buf = din;
>>> +    int total_size = bitlen >> 3;
>>> +    int chunk_size;
>>> +    int rx_len = 0;
>>> +    u32 data[(SPI_MSG_SIZE_MAX / 4) + 1] = { 0 };
>>> +    u32 val;
>>> +    int i;
>>> +
>>> +    debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__,
>>> dout, din,
>>> +          total_size, flags);
>>> +
>>> +    /*
>>> +     * This driver only supports half-duplex, so complain and bail out
>>> +     * upon full-duplex messages
>>> +     */
>>> +    if (dout && din) {
>>> +        printf("Only half-duplex SPI transfer supported\n");
>>> +        return -EIO;
>>> +    }
>>> +
>>> +    if (dout) {
>>> +        debug("TX-DATA: ");
>>> +        for (i = 0; i < total_size; i++)
>>> +            debug("%02x ", *ptr++);
>>> +        debug("\n");
>>> +    }
>>> +
>>> +    mt7621_spi_wait_till_ready(rs);
>>> +
>>> +    /*
>>> +     * Set CS active upon start of SPI message. This message can
>>> +     * be split upon multiple calls to this xfer function
>>> +     */
>>> +    if (flags & SPI_XFER_BEGIN)
>>> +        mt7621_spi_set_cs(rs, spi_chip_select(dev), 1);
>>> +
>>> +    while (total_size > 0) {
>>> +        /* Don't exceed the max xfer size */
>>> +        chunk_size = min_t(int, total_size, SPI_MSG_SIZE_MAX);
>>> +
>>> +        /*
>>> +         * We might have some TX data buffered from the last xfer
>>> +         * message. Make sure, that this does not exceed the max
>>> +         * xfer size
>>> +         */
>>> +        if (rs->tx_len > 4)
>>> +            chunk_size -= rs->tx_len;
>>> +        if (din)
>>> +            rx_len = chunk_size;
>>> +
>>> +        if (tx_buf) {
>>> +            /* Check if this message does not exceed the buffer */
>>> +            if ((chunk_size + rs->tx_len) > SPI_MSG_SIZE_OVERALL) {
>>> +                printf("TX message size too big (%d)\n",
>>> +                       chunk_size + rs->tx_len);
>>> +                return -EMSGSIZE;
>>> +            }
>>> +
>>> +            /*
>>> +             * Write all TX data into internal buffer to collect
>>> +             * all TX messages into one buffer (might be split into
>>> +             * multiple calls to this function)
>>> +             */
>>> +            for (i = 0; i < chunk_size; i++, rs->tx_len++) {
>>> +                rs->data[rs->tx_len / 4] |=
>>> +                    tx_buf[i] << (8 * (rs->tx_len & 3));
>>> +            }
>>> +        }
>>> +
>>> +        if (flags & SPI_XFER_END) {
>>> +            /* Write TX data into controller */
>>> +            if (rs->tx_len) {
>>> +                rs->data[0] = swab32(rs->data[0]);
>>> +                if (rs->tx_len < 4)
>>> +                    rs->data[0] >>= (4 - rs->tx_len) * 8;
>>> +
>>> +                for (i = 0; i < rs->tx_len; i += 4) {
>>> +                    mt7621_spi_write(rs,
>>> +                             MT7621_SPI_OPCODE + i,
>>> +                             rs->data[i / 4]);
>>> +                }
>>> +            }
>>> +
>>> +            /* Write length into controller */
>>> +            val = (min_t(int, rs->tx_len, 4) * 8) << 24;
>>> +            if (rs->tx_len > 4)
>>> +                val |= (rs->tx_len - 4) * 8;
>>> +            val |= (rx_len * 8) << 12;
>>> +            mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val);
>>> +
>>> +            /* Start the xfer */
>>> +            val = mt7621_spi_read(rs, MT7621_SPI_TRANS);
>>> +            val |= MT7621_SPI_TRANS_START;
>>> +            mt7621_spi_write(rs, MT7621_SPI_TRANS, val);
>>> +
>>> +            /* Wait until xfer is finished on bus */
>>> +            mt7621_spi_wait_till_ready(rs);
>>> +
>>> +            /* Reset TX length and TX buffer for next xfer */
>>> +            rs->tx_len = 0;
>>> +            memset(rs->data, 0, sizeof(rs->data));
>>> +        }
>>> +
>>> +        for (i = 0; i < rx_len; i += 4)
>>> +            data[i / 4] = mt7621_spi_read(rs, MT7621_SPI_DATA0 + i);
>>> +
>>> +        if (rx_len) {
>>> +            debug("RX-DATA: ");
>>> +            for (i = 0; i < rx_len; i++) {
>>> +                rx_buf[i] = data[i / 4] >> (8 * (i & 3));
>>> +                debug("%02x ", rx_buf[i]);
>>> +            }
>>> +            debug("\n");
>>> +        }
>>> +
>>> +        if (tx_buf)
>>> +            tx_buf += chunk_size;
>>> +        if (rx_buf)
>>> +            rx_buf += chunk_size;
>>> +        total_size -= chunk_size;
>>> +    }
>>> +
>>> +    /* Wait until xfer is finished on bus and de-assert CS */
>>> +    mt7621_spi_wait_till_ready(rs);
>>> +    if (flags & SPI_XFER_END)
>>> +        mt7621_spi_set_cs(rs, spi_chip_select(dev), 0);
>>> +
>>> +    return 0;
>>> +}
>>> +
>>> +static int mt76xx_spi_probe(struct udevice *dev)
>>> +{
>>> +    struct mt7621_spi *rs = dev_get_priv(dev);
>>> +
>>> +    rs->base = dev_remap_addr(dev);
>>> +    if (!rs->base)
>>> +        return -EINVAL;
>>> +
>>> +    rs->sys_freq = CONFIG_SYS_MIPS_TIMER_FREQ;
>>
>> you should create a minimal clock driver based on the system controller
>> block. The SPI clock has a separate bit for clock gating, so at least
>> one driver has to take care of enabling that clock. Also using
>> CONFIG_SYS_MIPS_TIMER_FREQ is a bad choice because it is a hard-coded
>> value which is usually the CPU clock divided by two. But CPU clock and
>> SYS clock are derived from PLL clock and can be configured with
>> different dividers.
> 
> Yes, this all sounds like a good idea. Unfortunately this work is not
> trivial, as (at least to my knowledge) no such clock driver exist
> in Linux right now. Documentation for the MT7688 is also very "limited"
> and the Linux DT has no clock nodes at all.
> 
> As time is very limited right now for such "improvements", would it
> be acceptable to add such a minimal clock driver at a later time?
> 
> Thanks,
> Stefan

ok, but at least use a DT property for the clock frequency or use a
fixed-clock driver, e.g.

spi_clk: spi-clk {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <3000000>;
	u-boot,dm-pre-reloc;
};
Stefan Roese Aug. 15, 2018, 12:06 p.m. | #5
On 15.08.2018 14:02, Daniel Schwierzeck wrote:
> 
> 
> On 15.08.2018 13:26, Stefan Roese wrote:
>> Hi Daniel,
>>
>> On 11.08.2018 18:59, Daniel Schwierzeck wrote:
>>> On 10.08.2018 08:56, Stefan Roese wrote:
>>>> This patch adds the SPI driver for the MediaTek MT7688 SoC (and
>>>> derivates). Its been tested on the LinkIt Smart 7688 and the Gardena
>>>> Smart Gateway with and SPI NOR on CS0 and on the Gardena Smart
>>>> Gateway additionally with an SPI NAND on CS1.
>>>>
>>>> Note that the SPI controller only supports a max transfer size of 32
>>>> bytes. This driver implementes a workaround to enable bigger xfer
>>>> sizes to speed up the transfer especially for the SPI NAND support.
>>>>
>>>> Signed-off-by: Stefan Roese <sr@denx.de>
>>>> Cc: Jagan Teki <jagan@openedev.com>
>>>> ---
>>>> v2:
>>>> - Add some macros instead of hardcoded numbers
>>>> - Move compatible DT struct down in the file
>>>>
>>>>    drivers/spi/Kconfig      |   8 +
>>>>    drivers/spi/Makefile     |   1 +
>>>>    drivers/spi/mt76xx_spi.c | 319 +++++++++++++++++++++++++++++++++++++++
>>>>    3 files changed, 328 insertions(+)
>>>>    create mode 100644 drivers/spi/mt76xx_spi.c
>>>>
>>>> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
>>>> index 9fbd26740d..6c4e50d3e9 100644
>>>> --- a/drivers/spi/Kconfig
>>>> +++ b/drivers/spi/Kconfig
>>>> @@ -116,6 +116,14 @@ config ICH_SPI
>>>>          access the SPI NOR flash on platforms embedding this Intel
>>>>          ICH IP core.
>>>>    +config MT76XX_SPI
>>>> +    bool "MediaTek MT76XX SPI driver"
>>>> +    depends on ARCH_MT7620
>>>> +    help
>>>> +      Enable the MT76XX SPI driver. This driver can be used to access
>>>> +      the SPI NOR flash on platforms embedding these MediaTek
>>>> +      SPI cores.
>>>> +
>>>>    config MVEBU_A3700_SPI
>>>>        bool "Marvell Armada 3700 SPI driver"
>>>>        select CLK_ARMADA_3720
>>>> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
>>>> index bdb5b5a02f..3d13ba1b21 100644
>>>> --- a/drivers/spi/Makefile
>>>> +++ b/drivers/spi/Makefile
>>>> @@ -33,6 +33,7 @@ obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
>>>>    obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o
>>>>    obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o
>>>>    obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
>>>> +obj-$(CONFIG_MT76XX_SPI) += mt76xx_spi.o
>>>>    obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o
>>>>    obj-$(CONFIG_MXC_SPI) += mxc_spi.o
>>>>    obj-$(CONFIG_MXS_SPI) += mxs_spi.o
>>>> diff --git a/drivers/spi/mt76xx_spi.c b/drivers/spi/mt76xx_spi.c
>>>> new file mode 100644
>>>> index 0000000000..f26b5341ce
>>>> --- /dev/null
>>>> +++ b/drivers/spi/mt76xx_spi.c
>>>> @@ -0,0 +1,319 @@
>>>> +// SPDX-License-Identifier: GPL-2.0+
>>>> +/*
>>>> + * Copyright (C) 2018 Stefan Roese <sr@denx.de>
>>>> + *
>>>> + * Derived from the Linux driver version drivers/spi/spi-mt7621.c
>>>> + *   Copyright (C) 2011 Sergiy <piratfm@gmail.com>
>>>> + *   Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
>>>> + *   Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name>
>>>> + */
>>>> +
>>>> +#include <common.h>
>>>> +#include <dm.h>
>>>> +#include <spi.h>
>>>> +#include <wait_bit.h>
>>>> +#include <linux/io.h>
>>>> +
>>>> +#define SPI_MSG_SIZE_MAX    32    /* SPI message chunk size */
>>>> +/* Enough for SPI NAND page read / write with page size 2048 bytes */
>>>> +#define SPI_MSG_SIZE_OVERALL    (2048 + 16)
>>>> +
>>>> +#define MT7621_SPI_TRANS    0x00
>>>> +#define MT7621_SPI_TRANS_START    BIT(8)
>>>> +#define MT7621_SPI_TRANS_BUSY    BIT(16)
>>>> +
>>>> +#define MT7621_SPI_OPCODE    0x04
>>>> +#define MT7621_SPI_DATA0    0x08
>>>> +#define MT7621_SPI_DATA4    0x18
>>>> +#define MT7621_SPI_MASTER    0x28
>>>> +#define MT7621_SPI_MOREBUF    0x2c
>>>> +#define MT7621_SPI_POLAR    0x38
>>>> +
>>>> +#define MT7621_LSB_FIRST    BIT(3)
>>>> +#define MT7621_CPOL        BIT(4)
>>>> +#define MT7621_CPHA        BIT(5)
>>>> +
>>>> +#define MASTER_MORE_BUFMODE    BIT(2)
>>>> +#define MASTER_RS_CLK_SEL    GENMASK(27, 16)
>>>> +#define MASTER_RS_CLK_SEL_SHIFT    16
>>>> +#define MASTER_RS_SLAVE_SEL    GENMASK(31, 29)
>>>> +
>>>> +struct mt7621_spi {
>>>> +    void __iomem *base;
>>>> +    unsigned int sys_freq;
>>>> +    u32 data[(SPI_MSG_SIZE_OVERALL / 4) + 1];
>>>> +    int tx_len;
>>>> +};
>>>> +
>>>> +static inline u32 mt7621_spi_read(struct mt7621_spi *rs, u32 reg)
>>>> +{
>>>> +    return ioread32(rs->base + reg);
>>>> +}
>>>> +
>>>> +static inline void mt7621_spi_write(struct mt7621_spi *rs, u32 reg,
>>>> u32 val)
>>>> +{
>>>> +    iowrite32(val, rs->base + reg);
>>>> +}
>>>> +
>>>> +static void mt7621_spi_reset(struct mt7621_spi *rs, int duplex)
>>>> +{
>>>> +    u32 master = mt7621_spi_read(rs, MT7621_SPI_MASTER);
>>>> +
>>>> +    master |= MASTER_RS_SLAVE_SEL;    /* CS control */
>>>> +    master |= MASTER_MORE_BUFMODE;    /* more_buf_mode */
>>>> +
>>>> +    mt7621_spi_write(rs, MT7621_SPI_MASTER, master);
>>>
>>> if you omit the (actually unneeded) I/O wrappers, you could simplify
>>> this with setbits_le32() (or setbits_32() for non-enforcing endianess)
>>
>> Yes, you are correct. All this is derived / copied from the Linux
>> driver. Even though the main xfer routine is pretty much different,
>> so it makes not much sense any more to stick with this IO wrappers
>> for code compatibility.
>>
>> I could work on a new version of this driver, omitting these IO
>> wrappers, if this is preferred. Or I could do this in a follow-up
>> patch, once this one is in mainline (time is a bit short right now).
> 
> follow-up patch would be ok, it was only meant as optional improvement.
> 
> But maybe the mt7621_ prefix could be replaced with mt76xx_ to be
> consistent with the source file name?
> 
>>
>>>> +}
>>>> +
>>>> +static void mt7621_spi_set_cs(struct mt7621_spi *rs, int cs, int
>>>> enable)
>>>> +{
>>>> +    u32 val = 0;
>>>> +
>>>> +    debug("%s: cs#%d -> %s\n", __func__, cs, enable ? "enable" :
>>>> "disable");
>>>> +    if (enable)
>>>> +        val = BIT(cs);
>>>> +    mt7621_spi_write(rs, MT7621_SPI_POLAR, val);
>>>> +}
>>>> +
>>>> +static int mt7621_spi_set_mode(struct udevice *bus, uint mode)
>>>> +{
>>>> +    struct mt7621_spi *rs = dev_get_priv(bus);
>>>> +    u32 reg;
>>>> +
>>>> +    debug("%s: mode=0x%08x\n", __func__, mode);
>>>> +    reg = mt7621_spi_read(rs, MT7621_SPI_MASTER);
>>>> +
>>>> +    reg &= ~MT7621_LSB_FIRST;
>>>> +    if (mode & SPI_LSB_FIRST)
>>>> +        reg |= MT7621_LSB_FIRST;
>>>> +
>>>> +    reg &= ~(MT7621_CPHA | MT7621_CPOL);
>>>> +    switch (mode & (SPI_CPOL | SPI_CPHA)) {
>>>> +    case SPI_MODE_0:
>>>> +        break;
>>>> +    case SPI_MODE_1:
>>>> +        reg |= MT7621_CPHA;
>>>> +        break;
>>>> +    case SPI_MODE_2:
>>>> +        reg |= MT7621_CPOL;
>>>> +        break;
>>>> +    case SPI_MODE_3:
>>>> +        reg |= MT7621_CPOL | MT7621_CPHA;
>>>> +        break;
>>>> +    }
>>>> +    mt7621_spi_write(rs, MT7621_SPI_MASTER, reg);
>>>> +
>>>> +    return 0;
>>>> +}
>>>> +
>>>> +static int mt7621_spi_set_speed(struct udevice *bus, uint speed)
>>>> +{
>>>> +    struct mt7621_spi *rs = dev_get_priv(bus);
>>>> +    u32 rate;
>>>> +    u32 reg;
>>>> +
>>>> +    debug("%s: speed=%d\n", __func__, speed);
>>>> +    rate = DIV_ROUND_UP(rs->sys_freq, speed);
>>>> +    debug("rate:%u\n", rate);
>>>> +
>>>> +    if (rate > 4097)
>>>> +        return -EINVAL;
>>>> +
>>>> +    if (rate < 2)
>>>> +        rate = 2;
>>>> +
>>>> +    reg = mt7621_spi_read(rs, MT7621_SPI_MASTER);
>>>> +    reg &= ~MASTER_RS_CLK_SEL;
>>>> +    reg |= (rate - 2) << MASTER_RS_CLK_SEL_SHIFT;
>>>> +    mt7621_spi_write(rs, MT7621_SPI_MASTER, reg);
>>>> +
>>>> +    return 0;
>>>> +}
>>>> +
>>>> +static inline int mt7621_spi_wait_till_ready(struct mt7621_spi *rs)
>>>> +{
>>>> +    int ret;
>>>> +
>>>> +    ret =  wait_for_bit_le32(rs->base + MT7621_SPI_TRANS,
>>>> +                 MT7621_SPI_TRANS_BUSY, 0, 10, 0);
>>>> +    if (ret)
>>>> +        pr_err("Timeout in %s!\n", __func__);
>>>> +
>>>> +    return ret;
>>>> +}
>>>> +
>>>> +static int mt7621_spi_xfer(struct udevice *dev, unsigned int bitlen,
>>>> +               const void *dout, void *din, unsigned long flags)
>>>> +{
>>>> +    struct udevice *bus = dev->parent;
>>>> +    struct mt7621_spi *rs = dev_get_priv(bus);
>>>> +    const u8 *tx_buf = dout;
>>>> +    u8 *ptr = (u8 *)dout;
>>>> +    u8 *rx_buf = din;
>>>> +    int total_size = bitlen >> 3;
>>>> +    int chunk_size;
>>>> +    int rx_len = 0;
>>>> +    u32 data[(SPI_MSG_SIZE_MAX / 4) + 1] = { 0 };
>>>> +    u32 val;
>>>> +    int i;
>>>> +
>>>> +    debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__,
>>>> dout, din,
>>>> +          total_size, flags);
>>>> +
>>>> +    /*
>>>> +     * This driver only supports half-duplex, so complain and bail out
>>>> +     * upon full-duplex messages
>>>> +     */
>>>> +    if (dout && din) {
>>>> +        printf("Only half-duplex SPI transfer supported\n");
>>>> +        return -EIO;
>>>> +    }
>>>> +
>>>> +    if (dout) {
>>>> +        debug("TX-DATA: ");
>>>> +        for (i = 0; i < total_size; i++)
>>>> +            debug("%02x ", *ptr++);
>>>> +        debug("\n");
>>>> +    }
>>>> +
>>>> +    mt7621_spi_wait_till_ready(rs);
>>>> +
>>>> +    /*
>>>> +     * Set CS active upon start of SPI message. This message can
>>>> +     * be split upon multiple calls to this xfer function
>>>> +     */
>>>> +    if (flags & SPI_XFER_BEGIN)
>>>> +        mt7621_spi_set_cs(rs, spi_chip_select(dev), 1);
>>>> +
>>>> +    while (total_size > 0) {
>>>> +        /* Don't exceed the max xfer size */
>>>> +        chunk_size = min_t(int, total_size, SPI_MSG_SIZE_MAX);
>>>> +
>>>> +        /*
>>>> +         * We might have some TX data buffered from the last xfer
>>>> +         * message. Make sure, that this does not exceed the max
>>>> +         * xfer size
>>>> +         */
>>>> +        if (rs->tx_len > 4)
>>>> +            chunk_size -= rs->tx_len;
>>>> +        if (din)
>>>> +            rx_len = chunk_size;
>>>> +
>>>> +        if (tx_buf) {
>>>> +            /* Check if this message does not exceed the buffer */
>>>> +            if ((chunk_size + rs->tx_len) > SPI_MSG_SIZE_OVERALL) {
>>>> +                printf("TX message size too big (%d)\n",
>>>> +                       chunk_size + rs->tx_len);
>>>> +                return -EMSGSIZE;
>>>> +            }
>>>> +
>>>> +            /*
>>>> +             * Write all TX data into internal buffer to collect
>>>> +             * all TX messages into one buffer (might be split into
>>>> +             * multiple calls to this function)
>>>> +             */
>>>> +            for (i = 0; i < chunk_size; i++, rs->tx_len++) {
>>>> +                rs->data[rs->tx_len / 4] |=
>>>> +                    tx_buf[i] << (8 * (rs->tx_len & 3));
>>>> +            }
>>>> +        }
>>>> +
>>>> +        if (flags & SPI_XFER_END) {
>>>> +            /* Write TX data into controller */
>>>> +            if (rs->tx_len) {
>>>> +                rs->data[0] = swab32(rs->data[0]);
>>>> +                if (rs->tx_len < 4)
>>>> +                    rs->data[0] >>= (4 - rs->tx_len) * 8;
>>>> +
>>>> +                for (i = 0; i < rs->tx_len; i += 4) {
>>>> +                    mt7621_spi_write(rs,
>>>> +                             MT7621_SPI_OPCODE + i,
>>>> +                             rs->data[i / 4]);
>>>> +                }
>>>> +            }
>>>> +
>>>> +            /* Write length into controller */
>>>> +            val = (min_t(int, rs->tx_len, 4) * 8) << 24;
>>>> +            if (rs->tx_len > 4)
>>>> +                val |= (rs->tx_len - 4) * 8;
>>>> +            val |= (rx_len * 8) << 12;
>>>> +            mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val);
>>>> +
>>>> +            /* Start the xfer */
>>>> +            val = mt7621_spi_read(rs, MT7621_SPI_TRANS);
>>>> +            val |= MT7621_SPI_TRANS_START;
>>>> +            mt7621_spi_write(rs, MT7621_SPI_TRANS, val);
>>>> +
>>>> +            /* Wait until xfer is finished on bus */
>>>> +            mt7621_spi_wait_till_ready(rs);
>>>> +
>>>> +            /* Reset TX length and TX buffer for next xfer */
>>>> +            rs->tx_len = 0;
>>>> +            memset(rs->data, 0, sizeof(rs->data));
>>>> +        }
>>>> +
>>>> +        for (i = 0; i < rx_len; i += 4)
>>>> +            data[i / 4] = mt7621_spi_read(rs, MT7621_SPI_DATA0 + i);
>>>> +
>>>> +        if (rx_len) {
>>>> +            debug("RX-DATA: ");
>>>> +            for (i = 0; i < rx_len; i++) {
>>>> +                rx_buf[i] = data[i / 4] >> (8 * (i & 3));
>>>> +                debug("%02x ", rx_buf[i]);
>>>> +            }
>>>> +            debug("\n");
>>>> +        }
>>>> +
>>>> +        if (tx_buf)
>>>> +            tx_buf += chunk_size;
>>>> +        if (rx_buf)
>>>> +            rx_buf += chunk_size;
>>>> +        total_size -= chunk_size;
>>>> +    }
>>>> +
>>>> +    /* Wait until xfer is finished on bus and de-assert CS */
>>>> +    mt7621_spi_wait_till_ready(rs);
>>>> +    if (flags & SPI_XFER_END)
>>>> +        mt7621_spi_set_cs(rs, spi_chip_select(dev), 0);
>>>> +
>>>> +    return 0;
>>>> +}
>>>> +
>>>> +static int mt76xx_spi_probe(struct udevice *dev)
>>>> +{
>>>> +    struct mt7621_spi *rs = dev_get_priv(dev);
>>>> +
>>>> +    rs->base = dev_remap_addr(dev);
>>>> +    if (!rs->base)
>>>> +        return -EINVAL;
>>>> +
>>>> +    rs->sys_freq = CONFIG_SYS_MIPS_TIMER_FREQ;
>>>
>>> you should create a minimal clock driver based on the system controller
>>> block. The SPI clock has a separate bit for clock gating, so at least
>>> one driver has to take care of enabling that clock. Also using
>>> CONFIG_SYS_MIPS_TIMER_FREQ is a bad choice because it is a hard-coded
>>> value which is usually the CPU clock divided by two. But CPU clock and
>>> SYS clock are derived from PLL clock and can be configured with
>>> different dividers.
>>
>> Yes, this all sounds like a good idea. Unfortunately this work is not
>> trivial, as (at least to my knowledge) no such clock driver exist
>> in Linux right now. Documentation for the MT7688 is also very "limited"
>> and the Linux DT has no clock nodes at all.
>>
>> As time is very limited right now for such "improvements", would it
>> be acceptable to add such a minimal clock driver at a later time?
>>
>> Thanks,
>> Stefan
> 
> ok, but at least use a DT property for the clock frequency or use a
> fixed-clock driver, e.g.
> 
> spi_clk: spi-clk {
> 	compatible = "fixed-clock";
> 	#clock-cells = <0>;
> 	clock-frequency = <3000000>;
> 	u-boot,dm-pre-reloc;
> };

Good idea. I'll work on a v3 in a short while and will add this and
replace the IO wrappers as well.

Thanks,
Stefan

Patch

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 9fbd26740d..6c4e50d3e9 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -116,6 +116,14 @@  config ICH_SPI
 	  access the SPI NOR flash on platforms embedding this Intel
 	  ICH IP core.
 
+config MT76XX_SPI
+	bool "MediaTek MT76XX SPI driver"
+	depends on ARCH_MT7620
+	help
+	  Enable the MT76XX SPI driver. This driver can be used to access
+	  the SPI NOR flash on platforms embedding these MediaTek
+	  SPI cores.
+
 config MVEBU_A3700_SPI
 	bool "Marvell Armada 3700 SPI driver"
 	select CLK_ARMADA_3720
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index bdb5b5a02f..3d13ba1b21 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -33,6 +33,7 @@  obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
 obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o
 obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o
 obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
+obj-$(CONFIG_MT76XX_SPI) += mt76xx_spi.o
 obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o
 obj-$(CONFIG_MXC_SPI) += mxc_spi.o
 obj-$(CONFIG_MXS_SPI) += mxs_spi.o
diff --git a/drivers/spi/mt76xx_spi.c b/drivers/spi/mt76xx_spi.c
new file mode 100644
index 0000000000..f26b5341ce
--- /dev/null
+++ b/drivers/spi/mt76xx_spi.c
@@ -0,0 +1,319 @@ 
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Stefan Roese <sr@denx.de>
+ *
+ * Derived from the Linux driver version drivers/spi/spi-mt7621.c
+ *   Copyright (C) 2011 Sergiy <piratfm@gmail.com>
+ *   Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
+ *   Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <spi.h>
+#include <wait_bit.h>
+#include <linux/io.h>
+
+#define SPI_MSG_SIZE_MAX	32	/* SPI message chunk size */
+/* Enough for SPI NAND page read / write with page size 2048 bytes */
+#define SPI_MSG_SIZE_OVERALL	(2048 + 16)
+
+#define MT7621_SPI_TRANS	0x00
+#define MT7621_SPI_TRANS_START	BIT(8)
+#define MT7621_SPI_TRANS_BUSY	BIT(16)
+
+#define MT7621_SPI_OPCODE	0x04
+#define MT7621_SPI_DATA0	0x08
+#define MT7621_SPI_DATA4	0x18
+#define MT7621_SPI_MASTER	0x28
+#define MT7621_SPI_MOREBUF	0x2c
+#define MT7621_SPI_POLAR	0x38
+
+#define MT7621_LSB_FIRST	BIT(3)
+#define MT7621_CPOL		BIT(4)
+#define MT7621_CPHA		BIT(5)
+
+#define MASTER_MORE_BUFMODE	BIT(2)
+#define MASTER_RS_CLK_SEL	GENMASK(27, 16)
+#define MASTER_RS_CLK_SEL_SHIFT	16
+#define MASTER_RS_SLAVE_SEL	GENMASK(31, 29)
+
+struct mt7621_spi {
+	void __iomem *base;
+	unsigned int sys_freq;
+	u32 data[(SPI_MSG_SIZE_OVERALL / 4) + 1];
+	int tx_len;
+};
+
+static inline u32 mt7621_spi_read(struct mt7621_spi *rs, u32 reg)
+{
+	return ioread32(rs->base + reg);
+}
+
+static inline void mt7621_spi_write(struct mt7621_spi *rs, u32 reg, u32 val)
+{
+	iowrite32(val, rs->base + reg);
+}
+
+static void mt7621_spi_reset(struct mt7621_spi *rs, int duplex)
+{
+	u32 master = mt7621_spi_read(rs, MT7621_SPI_MASTER);
+
+	master |= MASTER_RS_SLAVE_SEL;	/* CS control */
+	master |= MASTER_MORE_BUFMODE;	/* more_buf_mode */
+
+	mt7621_spi_write(rs, MT7621_SPI_MASTER, master);
+}
+
+static void mt7621_spi_set_cs(struct mt7621_spi *rs, int cs, int enable)
+{
+	u32 val = 0;
+
+	debug("%s: cs#%d -> %s\n", __func__, cs, enable ? "enable" : "disable");
+	if (enable)
+		val = BIT(cs);
+	mt7621_spi_write(rs, MT7621_SPI_POLAR, val);
+}
+
+static int mt7621_spi_set_mode(struct udevice *bus, uint mode)
+{
+	struct mt7621_spi *rs = dev_get_priv(bus);
+	u32 reg;
+
+	debug("%s: mode=0x%08x\n", __func__, mode);
+	reg = mt7621_spi_read(rs, MT7621_SPI_MASTER);
+
+	reg &= ~MT7621_LSB_FIRST;
+	if (mode & SPI_LSB_FIRST)
+		reg |= MT7621_LSB_FIRST;
+
+	reg &= ~(MT7621_CPHA | MT7621_CPOL);
+	switch (mode & (SPI_CPOL | SPI_CPHA)) {
+	case SPI_MODE_0:
+		break;
+	case SPI_MODE_1:
+		reg |= MT7621_CPHA;
+		break;
+	case SPI_MODE_2:
+		reg |= MT7621_CPOL;
+		break;
+	case SPI_MODE_3:
+		reg |= MT7621_CPOL | MT7621_CPHA;
+		break;
+	}
+	mt7621_spi_write(rs, MT7621_SPI_MASTER, reg);
+
+	return 0;
+}
+
+static int mt7621_spi_set_speed(struct udevice *bus, uint speed)
+{
+	struct mt7621_spi *rs = dev_get_priv(bus);
+	u32 rate;
+	u32 reg;
+
+	debug("%s: speed=%d\n", __func__, speed);
+	rate = DIV_ROUND_UP(rs->sys_freq, speed);
+	debug("rate:%u\n", rate);
+
+	if (rate > 4097)
+		return -EINVAL;
+
+	if (rate < 2)
+		rate = 2;
+
+	reg = mt7621_spi_read(rs, MT7621_SPI_MASTER);
+	reg &= ~MASTER_RS_CLK_SEL;
+	reg |= (rate - 2) << MASTER_RS_CLK_SEL_SHIFT;
+	mt7621_spi_write(rs, MT7621_SPI_MASTER, reg);
+
+	return 0;
+}
+
+static inline int mt7621_spi_wait_till_ready(struct mt7621_spi *rs)
+{
+	int ret;
+
+	ret =  wait_for_bit_le32(rs->base + MT7621_SPI_TRANS,
+				 MT7621_SPI_TRANS_BUSY, 0, 10, 0);
+	if (ret)
+		pr_err("Timeout in %s!\n", __func__);
+
+	return ret;
+}
+
+static int mt7621_spi_xfer(struct udevice *dev, unsigned int bitlen,
+			   const void *dout, void *din, unsigned long flags)
+{
+	struct udevice *bus = dev->parent;
+	struct mt7621_spi *rs = dev_get_priv(bus);
+	const u8 *tx_buf = dout;
+	u8 *ptr = (u8 *)dout;
+	u8 *rx_buf = din;
+	int total_size = bitlen >> 3;
+	int chunk_size;
+	int rx_len = 0;
+	u32 data[(SPI_MSG_SIZE_MAX / 4) + 1] = { 0 };
+	u32 val;
+	int i;
+
+	debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__, dout, din,
+	      total_size, flags);
+
+	/*
+	 * This driver only supports half-duplex, so complain and bail out
+	 * upon full-duplex messages
+	 */
+	if (dout && din) {
+		printf("Only half-duplex SPI transfer supported\n");
+		return -EIO;
+	}
+
+	if (dout) {
+		debug("TX-DATA: ");
+		for (i = 0; i < total_size; i++)
+			debug("%02x ", *ptr++);
+		debug("\n");
+	}
+
+	mt7621_spi_wait_till_ready(rs);
+
+	/*
+	 * Set CS active upon start of SPI message. This message can
+	 * be split upon multiple calls to this xfer function
+	 */
+	if (flags & SPI_XFER_BEGIN)
+		mt7621_spi_set_cs(rs, spi_chip_select(dev), 1);
+
+	while (total_size > 0) {
+		/* Don't exceed the max xfer size */
+		chunk_size = min_t(int, total_size, SPI_MSG_SIZE_MAX);
+
+		/*
+		 * We might have some TX data buffered from the last xfer
+		 * message. Make sure, that this does not exceed the max
+		 * xfer size
+		 */
+		if (rs->tx_len > 4)
+			chunk_size -= rs->tx_len;
+		if (din)
+			rx_len = chunk_size;
+
+		if (tx_buf) {
+			/* Check if this message does not exceed the buffer */
+			if ((chunk_size + rs->tx_len) > SPI_MSG_SIZE_OVERALL) {
+				printf("TX message size too big (%d)\n",
+				       chunk_size + rs->tx_len);
+				return -EMSGSIZE;
+			}
+
+			/*
+			 * Write all TX data into internal buffer to collect
+			 * all TX messages into one buffer (might be split into
+			 * multiple calls to this function)
+			 */
+			for (i = 0; i < chunk_size; i++, rs->tx_len++) {
+				rs->data[rs->tx_len / 4] |=
+					tx_buf[i] << (8 * (rs->tx_len & 3));
+			}
+		}
+
+		if (flags & SPI_XFER_END) {
+			/* Write TX data into controller */
+			if (rs->tx_len) {
+				rs->data[0] = swab32(rs->data[0]);
+				if (rs->tx_len < 4)
+					rs->data[0] >>= (4 - rs->tx_len) * 8;
+
+				for (i = 0; i < rs->tx_len; i += 4) {
+					mt7621_spi_write(rs,
+							 MT7621_SPI_OPCODE + i,
+							 rs->data[i / 4]);
+				}
+			}
+
+			/* Write length into controller */
+			val = (min_t(int, rs->tx_len, 4) * 8) << 24;
+			if (rs->tx_len > 4)
+				val |= (rs->tx_len - 4) * 8;
+			val |= (rx_len * 8) << 12;
+			mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val);
+
+			/* Start the xfer */
+			val = mt7621_spi_read(rs, MT7621_SPI_TRANS);
+			val |= MT7621_SPI_TRANS_START;
+			mt7621_spi_write(rs, MT7621_SPI_TRANS, val);
+
+			/* Wait until xfer is finished on bus */
+			mt7621_spi_wait_till_ready(rs);
+
+			/* Reset TX length and TX buffer for next xfer */
+			rs->tx_len = 0;
+			memset(rs->data, 0, sizeof(rs->data));
+		}
+
+		for (i = 0; i < rx_len; i += 4)
+			data[i / 4] = mt7621_spi_read(rs, MT7621_SPI_DATA0 + i);
+
+		if (rx_len) {
+			debug("RX-DATA: ");
+			for (i = 0; i < rx_len; i++) {
+				rx_buf[i] = data[i / 4] >> (8 * (i & 3));
+				debug("%02x ", rx_buf[i]);
+			}
+			debug("\n");
+		}
+
+		if (tx_buf)
+			tx_buf += chunk_size;
+		if (rx_buf)
+			rx_buf += chunk_size;
+		total_size -= chunk_size;
+	}
+
+	/* Wait until xfer is finished on bus and de-assert CS */
+	mt7621_spi_wait_till_ready(rs);
+	if (flags & SPI_XFER_END)
+		mt7621_spi_set_cs(rs, spi_chip_select(dev), 0);
+
+	return 0;
+}
+
+static int mt76xx_spi_probe(struct udevice *dev)
+{
+	struct mt7621_spi *rs = dev_get_priv(dev);
+
+	rs->base = dev_remap_addr(dev);
+	if (!rs->base)
+		return -EINVAL;
+
+	rs->sys_freq = CONFIG_SYS_MIPS_TIMER_FREQ;
+
+	mt7621_spi_reset(rs, 0);
+
+	return 0;
+}
+
+static const struct dm_spi_ops mt7621_spi_ops = {
+	.set_mode = mt7621_spi_set_mode,
+	.set_speed = mt7621_spi_set_speed,
+	.xfer = mt7621_spi_xfer,
+	/*
+	 * cs_info is not needed, since we require all chip selects to be
+	 * in the device tree explicitly
+	 */
+};
+
+static const struct udevice_id mt76xx_spi_ids[] = {
+	{ .compatible = "ralink,mt7621-spi" },
+	{ }
+};
+
+U_BOOT_DRIVER(mt76xx_spi) = {
+	.name = "mt76xx_spi",
+	.id = UCLASS_SPI,
+	.of_match = mt76xx_spi_ids,
+	.ops = &mt7621_spi_ops,
+	.priv_auto_alloc_size = sizeof(struct mt7621_spi),
+	.probe = mt76xx_spi_probe,
+};