[U-Boot,v2,44/53] clk: sunxi: Implement Ethernet resets

Message ID 20180810060711.6547-45-jagan@amarulasolutions.com
State Superseded
Delegated to: Jagannadha Sutradharudu Teki
Headers show
Series
  • clk: Add Allwinner CLK, RESET support
Related show

Commit Message

Jagan Teki Aug. 10, 2018, 6:07 a.m.
Implement Ethernet resets for all relevant Allwinner SoC
clock drivers via reset map descriptor table.

Cc: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 drivers/clk/sunxi/clk_a31.c  | 1 +
 drivers/clk/sunxi/clk_a64.c  | 1 +
 drivers/clk/sunxi/clk_a83t.c | 1 +
 drivers/clk/sunxi/clk_h3.c   | 1 +
 drivers/clk/sunxi/clk_r40.c  | 2 ++
 5 files changed, 6 insertions(+)

Patch

diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c
index d7a6b2421f..9023640913 100644
--- a/drivers/clk/sunxi/clk_a31.c
+++ b/drivers/clk/sunxi/clk_a31.c
@@ -63,6 +63,7 @@  static struct ccu_reset_map a31_resets[] = {
 	[RST_AHB1_MMC1]		= { 0x2c0, BIT(9) },
 	[RST_AHB1_MMC2]		= { 0x2c0, BIT(10) },
 	[RST_AHB1_MMC3]		= { 0x2c0, BIT(11) },
+	[RST_AHB1_EMAC]		= { 0x2c0, BIT(17) },
 	[RST_AHB1_SPI0]		= { 0x2c0, BIT(20) },
 	[RST_AHB1_SPI1]		= { 0x2c0, BIT(21) },
 	[RST_AHB1_SPI2]		= { 0x2c0, BIT(22) },
diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c
index 546ddcffa2..b2df499a24 100644
--- a/drivers/clk/sunxi/clk_a64.c
+++ b/drivers/clk/sunxi/clk_a64.c
@@ -54,6 +54,7 @@  static struct ccu_reset_map a64_resets[] = {
 	[RST_BUS_MMC0]		= { 0x2c0, BIT(8) },
 	[RST_BUS_MMC1]		= { 0x2c0, BIT(9) },
 	[RST_BUS_MMC2]		= { 0x2c0, BIT(10) },
+	[RST_BUS_EMAC]		= { 0x2c0, BIT(17) },
 	[RST_BUS_SPI0]		= { 0x2c0, BIT(20) },
 	[RST_BUS_SPI1]		= { 0x2c0, BIT(21) },
 	[RST_BUS_OTG]		= { 0x2c0, BIT(23) },
diff --git a/drivers/clk/sunxi/clk_a83t.c b/drivers/clk/sunxi/clk_a83t.c
index 593ce1ac1b..e1780d6729 100644
--- a/drivers/clk/sunxi/clk_a83t.c
+++ b/drivers/clk/sunxi/clk_a83t.c
@@ -47,6 +47,7 @@  static struct ccu_reset_map a83t_resets[] = {
 	[RST_BUS_MMC0]		= { 0x2c0, BIT(8) },
 	[RST_BUS_MMC1]		= { 0x2c0, BIT(9) },
 	[RST_BUS_MMC2]		= { 0x2c0, BIT(10) },
+	[RST_BUS_EMAC]		= { 0x2c0, BIT(17) },
 	[RST_BUS_OTG]		= { 0x2c0, BIT(24) },
 	[RST_BUS_EHCI0]		= { 0x2c0, BIT(26) },
 	[RST_BUS_EHCI1]		= { 0x2c0, BIT(27) },
diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c
index ff9f294097..88086580f4 100644
--- a/drivers/clk/sunxi/clk_h3.c
+++ b/drivers/clk/sunxi/clk_h3.c
@@ -60,6 +60,7 @@  static struct ccu_reset_map h3_resets[] = {
 	[RST_BUS_MMC0]		= { 0x2c0, BIT(8) },
 	[RST_BUS_MMC1]		= { 0x2c0, BIT(9) },
 	[RST_BUS_MMC2]		= { 0x2c0, BIT(10) },
+	[RST_BUS_EMAC]		= { 0x2c0, BIT(17) },
 	[RST_BUS_SPI0]		= { 0x2c0, BIT(20) },
 	[RST_BUS_SPI1]		= { 0x2c0, BIT(21) },
 	[RST_BUS_OTG]		= { 0x2c0, BIT(23) },
diff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c
index e5bddc77ee..cf00cf1011 100644
--- a/drivers/clk/sunxi/clk_r40.c
+++ b/drivers/clk/sunxi/clk_r40.c
@@ -66,6 +66,8 @@  static struct ccu_reset_map r40_resets[] = {
 	[RST_BUS_OHCI1]		= { 0x2c0, BIT(30) },
 	[RST_BUS_OHCI2]		= { 0x2c0, BIT(31) },
 
+	[RST_BUS_GMAC]		= { 0x2c0, BIT(17) },
+
 	[RST_BUS_UART0]		= { 0x2d8, BIT(16) },
 	[RST_BUS_UART1]		= { 0x2d8, BIT(17) },
 	[RST_BUS_UART2]		= { 0x2d8, BIT(18) },