[U-Boot,v2,43/53] clk: sunxi: Implement Ethernet clocks

Message ID 20180810060711.6547-44-jagan@amarulasolutions.com
State Superseded
Delegated to: Jagannadha Sutradharudu Teki
Headers show
Series
  • clk: Add Allwinner CLK, RESET support
Related show

Commit Message

Jagan Teki Aug. 10, 2018, 6:07 a.m.
Implement Ethernet clocks for all Allwinner SoCs
clock drivers via clock map descriptor table.

Cc: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 drivers/clk/sunxi/clk_a10.c  | 3 +++
 drivers/clk/sunxi/clk_a10s.c | 1 +
 drivers/clk/sunxi/clk_a31.c  | 1 +
 drivers/clk/sunxi/clk_a64.c  | 1 +
 drivers/clk/sunxi/clk_a83t.c | 1 +
 drivers/clk/sunxi/clk_h3.c   | 1 +
 drivers/clk/sunxi/clk_r40.c  | 2 ++
 7 files changed, 10 insertions(+)

Patch

diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c
index d145d37217..fc939a313d 100644
--- a/drivers/clk/sunxi/clk_a10.c
+++ b/drivers/clk/sunxi/clk_a10.c
@@ -22,11 +22,14 @@  static struct ccu_clk_map a10_clks[] = {
 	[CLK_AHB_MMC1]		= { 0x060, BIT(9), NULL },
 	[CLK_AHB_MMC2]		= { 0x060, BIT(10), NULL },
 	[CLK_AHB_MMC3]		= { 0x060, BIT(11), NULL },
+	[CLK_AHB_EMAC]		= { 0x060, BIT(17), NULL },
 	[CLK_AHB_SPI0]		= { 0x060, BIT(20), NULL },
 	[CLK_AHB_SPI1]		= { 0x060, BIT(21), NULL },
 	[CLK_AHB_SPI2]		= { 0x060, BIT(22), NULL },
 	[CLK_AHB_SPI3]		= { 0x060, BIT(23), NULL },
 
+	[CLK_AHB_GMAC]		= { 0x064, BIT(17), NULL },
+
 	[CLK_APB1_UART0]	= { 0x06c, BIT(16), NULL },
 	[CLK_APB1_UART1]	= { 0x06c, BIT(17), NULL },
 	[CLK_APB1_UART2]	= { 0x06c, BIT(18), NULL },
diff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c
index 5912043f19..6ce53dc27d 100644
--- a/drivers/clk/sunxi/clk_a10s.c
+++ b/drivers/clk/sunxi/clk_a10s.c
@@ -19,6 +19,7 @@  static struct ccu_clk_map a10s_clks[] = {
 	[CLK_AHB_MMC0]		= { 0x060, BIT(8), NULL },
 	[CLK_AHB_MMC1]		= { 0x060, BIT(9), NULL },
 	[CLK_AHB_MMC2]		= { 0x060, BIT(10), NULL },
+	[CLK_AHB_EMAC]		= { 0x060, BIT(17), NULL },
 	[CLK_AHB_SPI0]		= { 0x060, BIT(20), NULL },
 	[CLK_AHB_SPI1]		= { 0x060, BIT(21), NULL },
 	[CLK_AHB_SPI2]		= { 0x060, BIT(22), NULL },
diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c
index 288979a18f..d7a6b2421f 100644
--- a/drivers/clk/sunxi/clk_a31.c
+++ b/drivers/clk/sunxi/clk_a31.c
@@ -17,6 +17,7 @@  static struct ccu_clk_map a31_clks[] = {
 	[CLK_AHB1_MMC1]		= { 0x060, BIT(9), NULL },
 	[CLK_AHB1_MMC2]		= { 0x060, BIT(10), NULL },
 	[CLK_AHB1_MMC3]		= { 0x060, BIT(12), NULL },
+	[CLK_AHB1_EMAC]		= { 0x060, BIT(17), NULL },
 	[CLK_AHB1_SPI0]		= { 0x060, BIT(20), NULL },
 	[CLK_AHB1_SPI1]		= { 0x060, BIT(21), NULL },
 	[CLK_AHB1_SPI2]		= { 0x060, BIT(22), NULL },
diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c
index 344cfb59aa..546ddcffa2 100644
--- a/drivers/clk/sunxi/clk_a64.c
+++ b/drivers/clk/sunxi/clk_a64.c
@@ -16,6 +16,7 @@  static struct ccu_clk_map a64_clks[] = {
 	[CLK_BUS_MMC0]		= { 0x060, BIT(8), NULL },
 	[CLK_BUS_MMC1]		= { 0x060, BIT(9), NULL },
 	[CLK_BUS_MMC2]		= { 0x060, BIT(10), NULL },
+	[CLK_BUS_EMAC]		= { 0x060, BIT(17), NULL },
 	[CLK_BUS_SPI0]		= { 0x060, BIT(20), NULL },
 	[CLK_BUS_SPI1]		= { 0x060, BIT(21), NULL },
 	[CLK_BUS_OTG]		= { 0x060, BIT(23), NULL },
diff --git a/drivers/clk/sunxi/clk_a83t.c b/drivers/clk/sunxi/clk_a83t.c
index cf9455da97..593ce1ac1b 100644
--- a/drivers/clk/sunxi/clk_a83t.c
+++ b/drivers/clk/sunxi/clk_a83t.c
@@ -16,6 +16,7 @@  static struct ccu_clk_map a83t_clks[] = {
 	[CLK_BUS_MMC0]		= { 0x060, BIT(8), NULL },
 	[CLK_BUS_MMC1]		= { 0x060, BIT(9), NULL },
 	[CLK_BUS_MMC2]		= { 0x060, BIT(10), NULL },
+	[CLK_BUS_EMAC]		= { 0x060, BIT(17), NULL },
 	[CLK_BUS_OTG]		= { 0x060, BIT(24), NULL },
 	[CLK_BUS_EHCI0]		= { 0x060, BIT(26), NULL },
 	[CLK_BUS_EHCI1]		= { 0x060, BIT(27), NULL },
diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c
index 15d933a6c5..ff9f294097 100644
--- a/drivers/clk/sunxi/clk_h3.c
+++ b/drivers/clk/sunxi/clk_h3.c
@@ -16,6 +16,7 @@  static struct ccu_clk_map h3_clks[] = {
 	[CLK_BUS_MMC0]		= { 0x060, BIT(8), NULL },
 	[CLK_BUS_MMC1]		= { 0x060, BIT(9), NULL },
 	[CLK_BUS_MMC2]		= { 0x060, BIT(10), NULL },
+	[CLK_BUS_EMAC]		= { 0x060, BIT(17), NULL },
 	[CLK_BUS_SPI0]		= { 0x060, BIT(20), NULL },
 	[CLK_BUS_SPI1]		= { 0x060, BIT(21), NULL },
 	[CLK_BUS_OTG]		= { 0x060, BIT(23), NULL },
diff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c
index ee699d26ee..e5bddc77ee 100644
--- a/drivers/clk/sunxi/clk_r40.c
+++ b/drivers/clk/sunxi/clk_r40.c
@@ -25,6 +25,8 @@  static struct ccu_clk_map r40_clks[] = {
 	[CLK_BUS_OHCI1]		= { 0x060, BIT(30), NULL },
 	[CLK_BUS_OHCI2]		= { 0x060, BIT(31), NULL },
 
+	[CLK_BUS_GMAC]		= { 0x064, BIT(17), NULL },
+
 	[CLK_BUS_UART0]		= { 0x06c, BIT(16), NULL },
 	[CLK_BUS_UART1]		= { 0x06c, BIT(17), NULL },
 	[CLK_BUS_UART2]		= { 0x06c, BIT(18), NULL },