@@ -22,11 +22,14 @@ static struct ccu_clk_map a10_clks[] = {
[CLK_AHB_MMC1] = { 0x060, BIT(9), NULL },
[CLK_AHB_MMC2] = { 0x060, BIT(10), NULL },
[CLK_AHB_MMC3] = { 0x060, BIT(11), NULL },
+ [CLK_AHB_EMAC] = { 0x060, BIT(17), NULL },
[CLK_AHB_SPI0] = { 0x060, BIT(20), NULL },
[CLK_AHB_SPI1] = { 0x060, BIT(21), NULL },
[CLK_AHB_SPI2] = { 0x060, BIT(22), NULL },
[CLK_AHB_SPI3] = { 0x060, BIT(23), NULL },
+ [CLK_AHB_GMAC] = { 0x064, BIT(17), NULL },
+
[CLK_APB1_UART0] = { 0x06c, BIT(16), NULL },
[CLK_APB1_UART1] = { 0x06c, BIT(17), NULL },
[CLK_APB1_UART2] = { 0x06c, BIT(18), NULL },
@@ -19,6 +19,7 @@ static struct ccu_clk_map a10s_clks[] = {
[CLK_AHB_MMC0] = { 0x060, BIT(8), NULL },
[CLK_AHB_MMC1] = { 0x060, BIT(9), NULL },
[CLK_AHB_MMC2] = { 0x060, BIT(10), NULL },
+ [CLK_AHB_EMAC] = { 0x060, BIT(17), NULL },
[CLK_AHB_SPI0] = { 0x060, BIT(20), NULL },
[CLK_AHB_SPI1] = { 0x060, BIT(21), NULL },
[CLK_AHB_SPI2] = { 0x060, BIT(22), NULL },
@@ -17,6 +17,7 @@ static struct ccu_clk_map a31_clks[] = {
[CLK_AHB1_MMC1] = { 0x060, BIT(9), NULL },
[CLK_AHB1_MMC2] = { 0x060, BIT(10), NULL },
[CLK_AHB1_MMC3] = { 0x060, BIT(12), NULL },
+ [CLK_AHB1_EMAC] = { 0x060, BIT(17), NULL },
[CLK_AHB1_SPI0] = { 0x060, BIT(20), NULL },
[CLK_AHB1_SPI1] = { 0x060, BIT(21), NULL },
[CLK_AHB1_SPI2] = { 0x060, BIT(22), NULL },
@@ -16,6 +16,7 @@ static struct ccu_clk_map a64_clks[] = {
[CLK_BUS_MMC0] = { 0x060, BIT(8), NULL },
[CLK_BUS_MMC1] = { 0x060, BIT(9), NULL },
[CLK_BUS_MMC2] = { 0x060, BIT(10), NULL },
+ [CLK_BUS_EMAC] = { 0x060, BIT(17), NULL },
[CLK_BUS_SPI0] = { 0x060, BIT(20), NULL },
[CLK_BUS_SPI1] = { 0x060, BIT(21), NULL },
[CLK_BUS_OTG] = { 0x060, BIT(23), NULL },
@@ -16,6 +16,7 @@ static struct ccu_clk_map a83t_clks[] = {
[CLK_BUS_MMC0] = { 0x060, BIT(8), NULL },
[CLK_BUS_MMC1] = { 0x060, BIT(9), NULL },
[CLK_BUS_MMC2] = { 0x060, BIT(10), NULL },
+ [CLK_BUS_EMAC] = { 0x060, BIT(17), NULL },
[CLK_BUS_OTG] = { 0x060, BIT(24), NULL },
[CLK_BUS_EHCI0] = { 0x060, BIT(26), NULL },
[CLK_BUS_EHCI1] = { 0x060, BIT(27), NULL },
@@ -16,6 +16,7 @@ static struct ccu_clk_map h3_clks[] = {
[CLK_BUS_MMC0] = { 0x060, BIT(8), NULL },
[CLK_BUS_MMC1] = { 0x060, BIT(9), NULL },
[CLK_BUS_MMC2] = { 0x060, BIT(10), NULL },
+ [CLK_BUS_EMAC] = { 0x060, BIT(17), NULL },
[CLK_BUS_SPI0] = { 0x060, BIT(20), NULL },
[CLK_BUS_SPI1] = { 0x060, BIT(21), NULL },
[CLK_BUS_OTG] = { 0x060, BIT(23), NULL },
@@ -25,6 +25,8 @@ static struct ccu_clk_map r40_clks[] = {
[CLK_BUS_OHCI1] = { 0x060, BIT(30), NULL },
[CLK_BUS_OHCI2] = { 0x060, BIT(31), NULL },
+ [CLK_BUS_GMAC] = { 0x064, BIT(17), NULL },
+
[CLK_BUS_UART0] = { 0x06c, BIT(16), NULL },
[CLK_BUS_UART1] = { 0x06c, BIT(17), NULL },
[CLK_BUS_UART2] = { 0x06c, BIT(18), NULL },
Implement Ethernet clocks for all Allwinner SoCs clock drivers via clock map descriptor table. Cc: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> --- drivers/clk/sunxi/clk_a10.c | 3 +++ drivers/clk/sunxi/clk_a10s.c | 1 + drivers/clk/sunxi/clk_a31.c | 1 + drivers/clk/sunxi/clk_a64.c | 1 + drivers/clk/sunxi/clk_a83t.c | 1 + drivers/clk/sunxi/clk_h3.c | 1 + drivers/clk/sunxi/clk_r40.c | 2 ++ 7 files changed, 10 insertions(+)