From patchwork Fri Aug 10 06:07:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 955971 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="YPu1LWXc"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41mwD94dnDz9s7Q for ; Fri, 10 Aug 2018 16:28:09 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 62D42C21DA2; Fri, 10 Aug 2018 06:24:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id AE8BCC21E2B; Fri, 10 Aug 2018 06:14:31 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 852F0C21EB4; Fri, 10 Aug 2018 06:11:05 +0000 (UTC) Received: from mail-pf1-f195.google.com (mail-pf1-f195.google.com [209.85.210.195]) by lists.denx.de (Postfix) with ESMTPS id B67ABC21DD7 for ; Fri, 10 Aug 2018 06:11:01 +0000 (UTC) Received: by mail-pf1-f195.google.com with SMTP id k21-v6so4004058pff.11 for ; Thu, 09 Aug 2018 23:11:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=L/4J3mLpzbDIwe6RMQf/oxYo1CiXnvUScxfunYDEa9w=; b=YPu1LWXct2EyeIelQKueR2uYU5nA2W9AcUtr+10quzsssiHExvLKwDhzIoDUld71Tk hjhJ8ht+TWgmXmOGr/n0TKTiA59+gGXa6naf1dFiBMFERcQNT1Zpv5ZDdYg+GGq+XuTj j2WQk9UKaMrZhXHNDg9xJRaJFWkliTpB0V7ck= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=L/4J3mLpzbDIwe6RMQf/oxYo1CiXnvUScxfunYDEa9w=; b=SPVfjyG1B/8m62PMtvEie7LdUv8c335zdvippb36JZsrCAskhUPSvFc8xaJ1sHfM1s F6b4GOmYoJ4bviCrM3bAqVVkg6wMduEhMo+I3u16rYnVkTegz70fGrRalbSMttR4BuBH m3SSLzq+Xe3wZKF0ld+PD4D4hNxr+mX6UYTRcE9BvvbcxIy0LgsFR5WYuQDCD5M+2MBj uLfOVrsUfbLWuXC6orHz6nBSZBLY+AwEAaGeHUT13jgXq5OEYja7RoWS3VXGFyj1gDtL wlmPipAqi17BIs084Y24ijzARmP1YWKKMaFydVKtFu8QxjwZl8uEemludPIKI62GSNU+ 39tw== X-Gm-Message-State: AOUpUlEQclBVHzg5Ti3CSKan63o9OpMGnayQJ921cY53jZH8SPJ0DeoI UaAdYOCZfqWyrJMiwjQ05wgCJA== X-Google-Smtp-Source: AA+uWPzb6bwiKLZjHug6fnE6u+qIPl3+QbcrgGRjMl5rw4Rbpj4Ui4WMTBF5k9o6ImuDJEZv+JeHCQ== X-Received: by 2002:a63:e001:: with SMTP id e1-v6mr2467724pgh.380.1533881460359; Thu, 09 Aug 2018 23:11:00 -0700 (PDT) Received: from localhost.localdomain ([183.82.228.250]) by smtp.gmail.com with ESMTPSA id r23-v6sm16880975pfj.5.2018.08.09.23.10.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 09 Aug 2018 23:10:59 -0700 (PDT) From: Jagan Teki To: Maxime Ripard , Andre Przywara , Chen-Yu Tsai , Icenowy Zheng Date: Fri, 10 Aug 2018 11:37:10 +0530 Message-Id: <20180810060711.6547-53-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20180810060711.6547-1-jagan@amarulasolutions.com> References: <20180810060711.6547-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Cc: Tom Rini , u-boot@lists.denx.de, Joe Hershberger Subject: [U-Boot] [PATCH v2 52/53] net: sun8i_emac: Add EPHY CLK and RESET support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add EPHY CLK and RESET support for sun8i_emac driver to enable EPHY TX clock and EPHY reset pins via CLK and RESET framework. Cc: Joe Hershberger Cc: Lothar Felten Signed-off-by: Jagan Teki --- drivers/net/sun8i_emac.c | 72 ++++++++++++++++++++++++++++++---------- 1 file changed, 55 insertions(+), 17 deletions(-) diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index ad2d390f4e..bb97e6d7e9 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -134,7 +134,9 @@ struct emac_eth_dev { struct phy_device *phydev; struct mii_dev *bus; struct clk tx_clk; + struct clk ephy_clk; struct reset_ctl tx_rst; + struct reset_ctl ephy_rst; #ifdef CONFIG_DM_GPIO struct gpio_desc reset_gpio; #endif @@ -638,7 +640,6 @@ static int sun8i_eth_write_hwaddr(struct udevice *dev) static int sun8i_emac_board_setup(struct emac_eth_dev *priv) { - struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; int ret; ret = clk_enable(&priv->tx_clk); @@ -655,16 +656,20 @@ static int sun8i_emac_board_setup(struct emac_eth_dev *priv) } } - if (priv->variant == H3_EMAC) { - /* Only H3/H5 have clock controls for internal EPHY */ - if (priv->use_internal_phy) { - /* Set clock gating for ephy */ - setbits_le32(&ccm->bus_gate4, - BIT(AHB_GATE_OFFSET_EPHY)); - - /* Deassert EPHY */ - setbits_le32(&ccm->ahb_reset2_cfg, - BIT(AHB_RESET_OFFSET_EPHY)); + /* Only H3/H5 have clock controls for internal EPHY */ + if (clk_valid(&priv->ephy_clk)) { + ret = clk_enable(&priv->ephy_clk); + if (ret) { + dev_err(dev, "failed to enable EPHY TX clock\n"); + return ret; + } + } + + if (reset_valid(&priv->ephy_rst)) { + ret = reset_deassert(&priv->ephy_rst); + if (ret) { + dev_err(dev, "failed to deassert EPHY TX clock\n"); + return ret; } } @@ -819,6 +824,42 @@ static const struct eth_ops sun8i_emac_eth_ops = { .stop = sun8i_emac_eth_stop, }; +static int sun8i_get_ephy_nodes(struct emac_eth_dev *priv) +{ + int node, ret; + + /* look for mdio-mux node for internal PHY node */ + node = fdt_path_offset(gd->fdt_blob, + "/soc/ethernet@1c30000/mdio-mux/mdio@1/ethernet-phy@1"); + if (node < 0) { + debug("failed to get mdio-mux with internal PHY\n"); + return node; + } + + ret = fdt_node_check_compatible(gd->fdt_blob, node, + "allwinner,sun8i-h3-mdio-internal"); + if (ret < 0) { + debug("failed to find mdio-internal node\n"); + return ret; + } + + ret = clk_get_by_index_nodev(offset_to_ofnode(node), 0, &priv->ephy_clk); + if (ret) { + dev_err(dev, "failed to get EPHY TX clock\n"); + return ret; + } + + ret = reset_get_by_index_nodev(offset_to_ofnode(node), 0, &priv->ephy_rst); + if (ret) { + dev_err(dev, "failed to get EPHY TX reset\n"); + return ret; + } + + priv->use_internal_phy = true; + + return 0; +} + static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev) { struct sun8i_eth_pdata *sun8i_pdata = dev_get_platdata(dev); @@ -901,12 +942,9 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev) } if (priv->variant == H3_EMAC) { - int parent = fdt_parent_offset(gd->fdt_blob, offset); - - if (parent >= 0 && - !fdt_node_check_compatible(gd->fdt_blob, parent, - "allwinner,sun8i-h3-mdio-internal")) - priv->use_internal_phy = true; + ret = sun8i_get_ephy_nodes(priv); + if (ret) + return ret; } priv->interface = pdata->phy_interface;