[U-Boot,v2,19/53] clk: sunxi: Implement AHB bus MMC clocks

Message ID 20180810060711.6547-20-jagan@amarulasolutions.com
State Superseded
Delegated to: Jagannadha Sutradharudu Teki
Headers show
Series
  • clk: Add Allwinner CLK, RESET support
Related show

Commit Message

Jagan Teki Aug. 10, 2018, 6:06 a.m.
Implement AHB bus MMC clocks for all Allwinner SoC
clock drivers via clock map descriptor table.

Cc: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 drivers/clk/sunxi/clk_a10.c  | 4 ++++
 drivers/clk/sunxi/clk_a10s.c | 3 +++
 drivers/clk/sunxi/clk_a23.c  | 3 +++
 drivers/clk/sunxi/clk_a31.c  | 4 ++++
 drivers/clk/sunxi/clk_a64.c  | 3 +++
 drivers/clk/sunxi/clk_a83t.c | 3 +++
 drivers/clk/sunxi/clk_h3.c   | 3 +++
 drivers/clk/sunxi/clk_r40.c  | 4 ++++
 drivers/clk/sunxi/clk_v3s.c  | 3 +++
 9 files changed, 30 insertions(+)

Patch

diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c
index 7492e1367a..fb11231dd1 100644
--- a/drivers/clk/sunxi/clk_a10.c
+++ b/drivers/clk/sunxi/clk_a10.c
@@ -18,6 +18,10 @@  static struct ccu_clk_map a10_clks[] = {
 	[CLK_AHB_OHCI0]		= { 0x060, BIT(2), NULL },
 	[CLK_AHB_EHCI1]		= { 0x060, BIT(3), NULL },
 	[CLK_AHB_OHCI1]		= { 0x060, BIT(4), NULL },
+	[CLK_AHB_MMC0]		= { 0x060, BIT(8), NULL },
+	[CLK_AHB_MMC1]		= { 0x060, BIT(9), NULL },
+	[CLK_AHB_MMC2]		= { 0x060, BIT(10), NULL },
+	[CLK_AHB_MMC3]		= { 0x060, BIT(11), NULL },
 
 	[CLK_USB_OHCI0]		= { 0x0cc, BIT(6), NULL },
 	[CLK_USB_OHCI1]		= { 0x0cc, BIT(7), NULL },
diff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c
index 976595201f..bc4ae7352b 100644
--- a/drivers/clk/sunxi/clk_a10s.c
+++ b/drivers/clk/sunxi/clk_a10s.c
@@ -16,6 +16,9 @@  static struct ccu_clk_map a10s_clks[] = {
 	[CLK_AHB_OTG]		= { 0x060, BIT(0), NULL },
 	[CLK_AHB_EHCI]		= { 0x060, BIT(1), NULL },
 	[CLK_AHB_OHCI]		= { 0x060, BIT(2), NULL },
+	[CLK_AHB_MMC0]		= { 0x060, BIT(8), NULL },
+	[CLK_AHB_MMC1]		= { 0x060, BIT(9), NULL },
+	[CLK_AHB_MMC2]		= { 0x060, BIT(10), NULL },
 
 	[CLK_USB_OHCI]		= { 0x0cc, BIT(6), NULL },
 	[CLK_USB_PHY0]		= { 0x0cc, BIT(8), NULL },
diff --git a/drivers/clk/sunxi/clk_a23.c b/drivers/clk/sunxi/clk_a23.c
index ec9834e1a8..62770a58fe 100644
--- a/drivers/clk/sunxi/clk_a23.c
+++ b/drivers/clk/sunxi/clk_a23.c
@@ -13,6 +13,9 @@ 
 #include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
 
 static struct ccu_clk_map a23_clks[] = {
+	[CLK_BUS_MMC0]		= { 0x060, BIT(8), NULL },
+	[CLK_BUS_MMC1]		= { 0x060, BIT(9), NULL },
+	[CLK_BUS_MMC2]		= { 0x060, BIT(10), NULL },
 	[CLK_BUS_OTG]		= { 0x060, BIT(24), NULL },
 	[CLK_BUS_EHCI]		= { 0x060, BIT(26), NULL },
 	[CLK_BUS_OHCI]		= { 0x060, BIT(29), NULL },
diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c
index c6d82be120..f314feff69 100644
--- a/drivers/clk/sunxi/clk_a31.c
+++ b/drivers/clk/sunxi/clk_a31.c
@@ -13,6 +13,10 @@ 
 #include <dt-bindings/reset/sun6i-a31-ccu.h>
 
 static struct ccu_clk_map a31_clks[] = {
+	[CLK_AHB1_MMC0]		= { 0x060, BIT(8), NULL },
+	[CLK_AHB1_MMC1]		= { 0x060, BIT(9), NULL },
+	[CLK_AHB1_MMC2]		= { 0x060, BIT(10), NULL },
+	[CLK_AHB1_MMC3]		= { 0x060, BIT(12), NULL },
 	[CLK_AHB1_OTG]		= { 0x060, BIT(24), NULL },
 	[CLK_AHB1_EHCI0]	= { 0x060, BIT(26), NULL },
 	[CLK_AHB1_EHCI1]	= { 0x060, BIT(27), NULL },
diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c
index e5257b62c7..71f3510c74 100644
--- a/drivers/clk/sunxi/clk_a64.c
+++ b/drivers/clk/sunxi/clk_a64.c
@@ -13,6 +13,9 @@ 
 #include <dt-bindings/reset/sun50i-a64-ccu.h>
 
 static struct ccu_clk_map a64_clks[] = {
+	[CLK_BUS_MMC0]		= { 0x060, BIT(8), NULL },
+	[CLK_BUS_MMC1]		= { 0x060, BIT(9), NULL },
+	[CLK_BUS_MMC2]		= { 0x060, BIT(10), NULL },
 	[CLK_BUS_OTG]		= { 0x060, BIT(23), NULL },
 	[CLK_BUS_EHCI0]		= { 0x060, BIT(24), NULL },
 	[CLK_BUS_EHCI1]		= { 0x060, BIT(25), NULL },
diff --git a/drivers/clk/sunxi/clk_a83t.c b/drivers/clk/sunxi/clk_a83t.c
index 58d28eb6ad..cc18975a06 100644
--- a/drivers/clk/sunxi/clk_a83t.c
+++ b/drivers/clk/sunxi/clk_a83t.c
@@ -13,6 +13,9 @@ 
 #include <dt-bindings/reset/sun8i-a83t-ccu.h>
 
 static struct ccu_clk_map a83t_clks[] = {
+	[CLK_BUS_MMC0]		= { 0x060, BIT(8), NULL },
+	[CLK_BUS_MMC1]		= { 0x060, BIT(9), NULL },
+	[CLK_BUS_MMC2]		= { 0x060, BIT(10), NULL },
 	[CLK_BUS_OTG]		= { 0x060, BIT(24), NULL },
 	[CLK_BUS_EHCI0]		= { 0x060, BIT(26), NULL },
 	[CLK_BUS_EHCI1]		= { 0x060, BIT(27), NULL },
diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c
index 0b7f4947dd..85dd06ee2d 100644
--- a/drivers/clk/sunxi/clk_h3.c
+++ b/drivers/clk/sunxi/clk_h3.c
@@ -13,6 +13,9 @@ 
 #include <dt-bindings/reset/sun8i-h3-ccu.h>
 
 static struct ccu_clk_map h3_clks[] = {
+	[CLK_BUS_MMC0]		= { 0x060, BIT(8), NULL },
+	[CLK_BUS_MMC1]		= { 0x060, BIT(9), NULL },
+	[CLK_BUS_MMC2]		= { 0x060, BIT(10), NULL },
 	[CLK_BUS_OTG]		= { 0x060, BIT(23), NULL },
 	[CLK_BUS_EHCI0]		= { 0x060, BIT(24), NULL },
 	[CLK_BUS_EHCI1]		= { 0x060, BIT(25), NULL },
diff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c
index 746d6734b2..006aa138b6 100644
--- a/drivers/clk/sunxi/clk_r40.c
+++ b/drivers/clk/sunxi/clk_r40.c
@@ -13,6 +13,10 @@ 
 #include <dt-bindings/reset/sun8i-r40-ccu.h>
 
 static struct ccu_clk_map r40_clks[] = {
+	[CLK_BUS_MMC0]		= { 0x060, BIT(8), NULL },
+	[CLK_BUS_MMC1]		= { 0x060, BIT(9), NULL },
+	[CLK_BUS_MMC2]		= { 0x060, BIT(10), NULL },
+	[CLK_BUS_MMC3]		= { 0x060, BIT(11), NULL },
 	[CLK_BUS_OTG]		= { 0x060, BIT(25), NULL },
 	[CLK_BUS_EHCI0]		= { 0x060, BIT(26), NULL },
 	[CLK_BUS_EHCI1]		= { 0x060, BIT(27), NULL },
diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c
index 2494518798..ab2cc45640 100644
--- a/drivers/clk/sunxi/clk_v3s.c
+++ b/drivers/clk/sunxi/clk_v3s.c
@@ -13,6 +13,9 @@ 
 #include <dt-bindings/reset/sun8i-v3s-ccu.h>
 
 static struct ccu_clk_map v3s_clks[] = {
+	[CLK_BUS_MMC0]		= { 0x060, BIT(8), NULL },
+	[CLK_BUS_MMC1]		= { 0x060, BIT(9), NULL },
+	[CLK_BUS_MMC2]		= { 0x060, BIT(10), NULL },
 	[CLK_BUS_OTG]		= { 0x060, BIT(24), NULL },
 
 	[CLK_USB_PHY0]          = { 0x0cc, BIT(8), NULL },