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Thu, 09 Aug 2018 23:08:04 -0700 (PDT) Received: from localhost.localdomain ([183.82.228.250]) by smtp.gmail.com with ESMTPSA id r23-v6sm16880975pfj.5.2018.08.09.23.08.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 09 Aug 2018 23:08:03 -0700 (PDT) From: Jagan Teki To: Maxime Ripard , Andre Przywara , Chen-Yu Tsai , Icenowy Zheng Date: Fri, 10 Aug 2018 11:36:25 +0530 Message-Id: <20180810060711.6547-8-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20180810060711.6547-1-jagan@amarulasolutions.com> References: <20180810060711.6547-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Cc: Tom Rini , u-boot@lists.denx.de Subject: [U-Boot] [PATCH v2 07/53] clk: sunxi: Add Allwinner A10s/A13 CLK driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add initial clock driver for Allwinner A10s/A13. - Implement USB ahb and USB clocks via ccu_clk_map descriptor for A10s/A13, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB resets via ccu_reset_map descriptor for A10s/A13, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki --- drivers/clk/sunxi/Kconfig | 7 ++++ drivers/clk/sunxi/Makefile | 1 + drivers/clk/sunxi/clk_a10s.c | 74 ++++++++++++++++++++++++++++++++++++ 3 files changed, 82 insertions(+) create mode 100644 drivers/clk/sunxi/clk_a10s.c diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig index fbbf94ef55..b228c2fa3a 100644 --- a/drivers/clk/sunxi/Kconfig +++ b/drivers/clk/sunxi/Kconfig @@ -16,6 +16,13 @@ config CLK_SUN4I_A10 This enables common clock driver support for platforms based on Allwinner A10/A20 SoC. +config CLK_SUN5I_A10S + bool "Clock driver for Allwinner A10s/A13" + default MACH_SUN5I + help + This enables common clock driver support for platforms based + on Allwinner A10s/A13 SoC. + config CLK_SUN8I_H3 bool "Clock driver for Allwinner H3/H5" default MACH_SUNXI_H3_H5 diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile index bba830922f..466d4b79d6 100644 --- a/drivers/clk/sunxi/Makefile +++ b/drivers/clk/sunxi/Makefile @@ -7,5 +7,6 @@ obj-$(CONFIG_CLK_SUNXI) += clk_sunxi.o obj-$(CONFIG_CLK_SUN4I_A10) += clk_a10.o +obj-$(CONFIG_CLK_SUN5I_A10S) += clk_a10s.o obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o diff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c new file mode 100644 index 0000000000..976595201f --- /dev/null +++ b/drivers/clk/sunxi/clk_a10s.c @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 Amarula Solutions. + * Author: Jagan Teki + */ + +#include +#include +#include +#include +#include +#include +#include + +static struct ccu_clk_map a10s_clks[] = { + [CLK_AHB_OTG] = { 0x060, BIT(0), NULL }, + [CLK_AHB_EHCI] = { 0x060, BIT(1), NULL }, + [CLK_AHB_OHCI] = { 0x060, BIT(2), NULL }, + + [CLK_USB_OHCI] = { 0x0cc, BIT(6), NULL }, + [CLK_USB_PHY0] = { 0x0cc, BIT(8), NULL }, + [CLK_USB_PHY1] = { 0x0cc, BIT(9), NULL }, +}; + +static struct ccu_reset_map a10s_resets[] = { + [RST_USB_PHY0] = { 0x0cc, BIT(0) }, + [RST_USB_PHY1] = { 0x0cc, BIT(1) }, +}; + +static const struct ccu_desc sun5i_a10s_ccu_desc = { + .clks = a10s_clks, + .num_clks = ARRAY_SIZE(a10s_clks), + + .resets = a10s_resets, + .num_resets = ARRAY_SIZE(a10s_resets), +}; + +static int a10s_clk_probe(struct udevice *dev) +{ + struct sunxi_clk_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr_ptr(dev); + if (!priv->base) + return -ENOMEM; + + priv->desc = (const struct ccu_desc *)dev_get_driver_data(dev); + if (!priv->desc) + return -EINVAL; + + return 0; +} + +static int a10s_clk_bind(struct udevice *dev) +{ + return sunxi_reset_bind(dev, 10); +} + +static const struct udevice_id a10s_clk_ids[] = { + { .compatible = "allwinner,sun5i-a10s-ccu", + .data = (ulong)&sun5i_a10s_ccu_desc }, + { .compatible = "allwinner,sun5i-a13-ccu", + .data = (ulong)&sun5i_a10s_ccu_desc }, + { } +}; + +U_BOOT_DRIVER(clk_sun5i_a10s) = { + .name = "sun5i_a10s_ccu", + .id = UCLASS_CLK, + .of_match = a10s_clk_ids, + .priv_auto_alloc_size = sizeof(struct sunxi_clk_priv), + .ops = &sunxi_clk_ops, + .probe = a10s_clk_probe, + .bind = a10s_clk_bind, +};