From patchwork Fri Aug 10 06:06:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 955956 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="faaRkvN5"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41mvzS1XpNz9s7Q for ; Fri, 10 Aug 2018 16:17:07 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id A9A3BC21EF1; Fri, 10 Aug 2018 06:15:42 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id B8FF1C21E56; Fri, 10 Aug 2018 06:10:01 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id D3953C21E2F; Fri, 10 Aug 2018 06:08:39 +0000 (UTC) Received: from mail-pl0-f67.google.com (mail-pl0-f67.google.com [209.85.160.67]) by lists.denx.de (Postfix) with ESMTPS id E479EC21E16 for ; Fri, 10 Aug 2018 06:08:34 +0000 (UTC) Received: by mail-pl0-f67.google.com with SMTP id w19-v6so3590151ply.8 for ; Thu, 09 Aug 2018 23:08:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BVCFOji7gHqub8o/VdQ16BYMIMKk7AZtaDxPR2oBiXg=; b=faaRkvN5ZuIscFLvyzNv4gnHjwMkhj30HFm1kd3Q9+GXewQsehAn2FBV/CFY04zx2D bEXhhs6m3A1rTGXSl8jdDE43A/cRAgoyD6TvQm32wXqXU+U+fC8Hj29ZfJKT5hQTKV9G aKSQt7ohoE7e4Z58K4IkaOtxNNLlE+aBpPfNY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BVCFOji7gHqub8o/VdQ16BYMIMKk7AZtaDxPR2oBiXg=; b=mrRmid237S4wWfx5erAscfbOSNOQTPgWfIkvrFwD+j65LRAYe1Pukogj9gDuo9QZkx TLopFVLe9wH7WAQndhDiYD0VhXFqqhq3UtH8JQlFAfVeDVen9wB1TFMEeHDXa+9695pW jjUrMBmGN2i7zRw+LgMPoY45AuBnMVhdVgSa++OyzbtztSiByTdR5JzYXGxSKiJgCDt6 0VbBhB+fEEzvRm8U/HmyOHkC5TlGinxyUlCJWtNcwpGlwR4Bsy2AZ27jL+w1BgHrt/vn lvBtiPqAuweIKDrY+lR3a2a9HPDh/sgFpcs+H0vry1SoP7Kjp7hpAasP5PIfh/NR1ids A8ZA== X-Gm-Message-State: AOUpUlEGEJUXicubaETZEn/3PzbQt+ogA0M1si/7edySKK3YyoBdBccN 9jGqn+JUEDm2CMVsppOKH6oMUA== X-Google-Smtp-Source: AA+uWPxW3p3m1XKRBsuqij4hy44AfGauCmJh5fgHpAZ8VyEqobiOlaqyz7QscNgR6kT0hMonSSoCSw== X-Received: by 2002:a17:902:261:: with SMTP id 88-v6mr4889937plc.331.1533881313540; Thu, 09 Aug 2018 23:08:33 -0700 (PDT) Received: from localhost.localdomain ([183.82.228.250]) by smtp.gmail.com with ESMTPSA id r23-v6sm16880975pfj.5.2018.08.09.23.08.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 09 Aug 2018 23:08:33 -0700 (PDT) From: Jagan Teki To: Maxime Ripard , Andre Przywara , Chen-Yu Tsai , Icenowy Zheng Date: Fri, 10 Aug 2018 11:36:33 +0530 Message-Id: <20180810060711.6547-16-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20180810060711.6547-1-jagan@amarulasolutions.com> References: <20180810060711.6547-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Cc: Tom Rini , u-boot@lists.denx.de Subject: [U-Boot] [PATCH v2 15/53] musb-new: sunxi: Use CLK and RESET support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Now clock and reset drivers are available for respective SoC's so use clk and reset ops on musb driver. Signed-off-by: Jagan Teki --- drivers/usb/musb-new/sunxi.c | 82 +++++++++++++++++++++++------------- 1 file changed, 53 insertions(+), 29 deletions(-) diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c index 9f71b84fd1..440be83f4e 100644 --- a/drivers/usb/musb-new/sunxi.c +++ b/drivers/usb/musb-new/sunxi.c @@ -16,9 +16,11 @@ * This file is part of the Inventra Controller Driver for Linux. */ #include +#include #include #include #include +#include #include #include #include @@ -78,16 +80,15 @@ struct sunxi_musb_config { struct musb_hdrc_config *config; - u8 rst_bit; - u8 clkgate_bit; }; struct sunxi_glue { struct musb_host_data mdata; - struct sunxi_ccm_reg *ccm; struct sunxi_musb_config *cfg; struct device dev; struct phy phy; + struct clk clocks; + struct reset_ctl resets; }; #define to_sunxi_glue(d) container_of(d, struct sunxi_glue, dev) @@ -291,6 +292,18 @@ static int sunxi_musb_init(struct musb *musb) pr_debug("%s():\n", __func__); + ret = clk_enable(&glue->clocks); + if (ret) { + dev_err(dev, "failed to enable clock\n"); + return ret; + } + + ret = reset_deassert(&glue->resets); + if (ret) { + dev_err(dev, "failed to deassert reset\n"); + return ret; + } + ret = generic_phy_init(&glue->phy); if (ret) { pr_err("failed to init USB PHY\n"); @@ -299,17 +312,6 @@ static int sunxi_musb_init(struct musb *musb) musb->isr = sunxi_musb_interrupt; - setbits_le32(&glue->ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_USB0)); - if (glue->cfg->clkgate_bit) - setbits_le32(&glue->ccm->ahb_gate0, - BIT(glue->cfg->clkgate_bit)); -#ifdef CONFIG_SUNXI_GEN_SUN6I - setbits_le32(&glue->ccm->ahb_reset0_cfg, BIT(AHB_GATE_OFFSET_USB0)); - if (glue->cfg->rst_bit) - setbits_le32(&glue->ccm->ahb_reset0_cfg, - BIT(glue->cfg->rst_bit)); -#endif - USBC_ConfigFIFO_Base(); USBC_EnableDpDmPullUp(musb->mregs); USBC_EnableIdPullUp(musb->mregs); @@ -339,16 +341,17 @@ static int sunxi_musb_exit(struct musb *musb) } } -#ifdef CONFIG_SUNXI_GEN_SUN6I - clrbits_le32(&glue->ccm->ahb_reset0_cfg, BIT(AHB_GATE_OFFSET_USB0)); - if (glue->cfg->rst_bit) - clrbits_le32(&glue->ccm->ahb_reset0_cfg, - BIT(glue->cfg->rst_bit)); -#endif - clrbits_le32(&glue->ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_USB0)); - if (glue->cfg->clkgate_bit) - clrbits_le32(&glue->ccm->ahb_gate0, - BIT(glue->cfg->clkgate_bit)); + ret = reset_assert(&glue->resets); + if (ret) { + dev_err(dev, "failed to deassert reset\n"); + return ret; + } + + ret = clk_disable(&glue->clocks); + if (ret) { + dev_err(dev, "failed to enable clock\n"); + return ret; + } return 0; } @@ -433,6 +436,7 @@ static int musb_usb_probe(struct udevice *dev) struct usb_bus_priv *priv = dev_get_uclass_priv(dev); struct musb_hdrc_platform_data pdata; void *base = dev_read_addr_ptr(dev); + int clock_nb, reset_nb; int ret; if (!base) @@ -442,9 +446,31 @@ static int musb_usb_probe(struct udevice *dev) if (!glue->cfg) return -EINVAL; - glue->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - if (IS_ERR(glue->ccm)) - return PTR_ERR(glue->ccm); + clock_nb = ofnode_count_phandle_with_args(dev_ofnode(dev), "clocks", + "#clock-cells"); + if (clock_nb < 0) { + dev_err(dev, "failed to get clock phandle(%d)\n", clock_nb); + return clock_nb; + } + + ret = clk_get_by_index(dev, 0, &glue->clocks); + if (ret) { + dev_err(dev, "failed to get clock 0\n"); + clk_free(&glue->clocks); + } + + reset_nb = ofnode_count_phandle_with_args(dev_ofnode(dev), "resets", + "#reset-cells"); + if (reset_nb < 0) { + dev_err(dev, "failed to get reset phandle(%d)\n", clock_nb); + return reset_nb; + } + + ret = reset_get_by_index(dev, 0, &glue->resets); + if (ret) { + dev_err(dev, "failed to get reset 0\n"); + reset_free(&glue->resets); + } ret = generic_phy_get_by_name(dev, "usb", &glue->phy); if (ret) { @@ -499,8 +525,6 @@ static const struct sunxi_musb_config sun4i_a10_cfg = { static const struct sunxi_musb_config sun8i_h3_cfg = { .config = &musb_config_h3, - .rst_bit = 23, - .clkgate_bit = 23, }; static const struct udevice_id sunxi_musb_ids[] = {