[U-Boot,v2,12/53] clk: sunxi: Add Allwinner R40 CLK driver

Message ID 20180810060711.6547-13-jagan@amarulasolutions.com
State Superseded
Delegated to: Jagannadha Sutradharudu Teki
Headers show
Series
  • clk: Add Allwinner CLK, RESET support
Related show

Commit Message

Jagan Teki Aug. 10, 2018, 6:06 a.m.
Add initial clock driver for Allwinner R40.

- Implement USB bus and USB clocks via ccu_clk_map descriptor
  for R40, so it can accessed in common clk enable and disable
  functions from clk_sunxi.c
- Implement USB bus and USB resets via ccu_reset_map descriptor
  for R40, so it can accessed in common reset deassert and assert
  functions from reset-sunxi.c

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 drivers/clk/sunxi/Kconfig   |  7 +++
 drivers/clk/sunxi/Makefile  |  1 +
 drivers/clk/sunxi/clk_r40.c | 89 +++++++++++++++++++++++++++++++++++++
 3 files changed, 97 insertions(+)
 create mode 100644 drivers/clk/sunxi/clk_r40.c

Patch

diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig
index 90af70d171..c45a4ba378 100644
--- a/drivers/clk/sunxi/Kconfig
+++ b/drivers/clk/sunxi/Kconfig
@@ -44,6 +44,13 @@  config CLK_SUN8I_A83T
 	  This enables common clock driver support for platforms based
 	  on Allwinner A83T SoC.
 
+config CLK_SUN8I_R40
+	bool "Clock driver for Allwinner R40"
+	default MACH_SUN8I_R40
+	help
+	  This enables common clock driver support for platforms based
+	  on Allwinner R40 SoC.
+
 config CLK_SUN8I_H3
 	bool "Clock driver for Allwinner H3/H5"
 	default MACH_SUNXI_H3_H5
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index 4a254c8671..61f8b87396 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -11,5 +11,6 @@  obj-$(CONFIG_CLK_SUN5I_A10S) += clk_a10s.o
 obj-$(CONFIG_CLK_SUN6I_A31) += clk_a31.o
 obj-$(CONFIG_CLK_SUN8I_A23) += clk_a23.o
 obj-$(CONFIG_CLK_SUN8I_A83T) += clk_a83t.o
+obj-$(CONFIG_CLK_SUN8I_R40) += clk_r40.o
 obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o
 obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o
diff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c
new file mode 100644
index 0000000000..746d6734b2
--- /dev/null
+++ b/drivers/clk/sunxi/clk_r40.c
@@ -0,0 +1,89 @@ 
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2018 Amarula Solutions.
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/arch/ccu.h>
+#include <dt-bindings/clock/sun8i-r40-ccu.h>
+#include <dt-bindings/reset/sun8i-r40-ccu.h>
+
+static struct ccu_clk_map r40_clks[] = {
+	[CLK_BUS_OTG]		= { 0x060, BIT(25), NULL },
+	[CLK_BUS_EHCI0]		= { 0x060, BIT(26), NULL },
+	[CLK_BUS_EHCI1]		= { 0x060, BIT(27), NULL },
+	[CLK_BUS_EHCI2]		= { 0x060, BIT(28), NULL },
+	[CLK_BUS_OHCI0]		= { 0x060, BIT(29), NULL },
+	[CLK_BUS_OHCI1]		= { 0x060, BIT(30), NULL },
+	[CLK_BUS_OHCI2]		= { 0x060, BIT(31), NULL },
+
+
+	[CLK_USB_PHY0]		= { 0x0cc, BIT(8), NULL },
+	[CLK_USB_PHY1]		= { 0x0cc, BIT(9), NULL },
+	[CLK_USB_PHY2]		= { 0x0cc, BIT(10), NULL },
+	[CLK_USB_OHCI0]		= { 0x0cc, BIT(16), NULL },
+	[CLK_USB_OHCI1]		= { 0x0cc, BIT(17), NULL },
+	[CLK_USB_OHCI2]		= { 0x0cc, BIT(18), NULL },
+};
+
+static struct ccu_reset_map r40_resets[] = {
+	[RST_USB_PHY0]		= { 0x0cc, BIT(0) },
+	[RST_USB_PHY1]		= { 0x0cc, BIT(1) },
+	[RST_USB_PHY2]		= { 0x0cc, BIT(2) },
+
+	[RST_BUS_OTG]		= { 0x2c0, BIT(25) },
+	[RST_BUS_EHCI0]		= { 0x2c0, BIT(26) },
+	[RST_BUS_EHCI1]		= { 0x2c0, BIT(27) },
+	[RST_BUS_EHCI2]		= { 0x2c0, BIT(28) },
+	[RST_BUS_OHCI0]		= { 0x2c0, BIT(29) },
+	[RST_BUS_OHCI1]		= { 0x2c0, BIT(30) },
+	[RST_BUS_OHCI2]		= { 0x2c0, BIT(31) },
+};
+
+static const struct ccu_desc sun8i_r40_ccu_desc = {
+	.clks = r40_clks,
+	.num_clks = ARRAY_SIZE(r40_clks),
+
+	.resets = r40_resets,
+	.num_resets =  ARRAY_SIZE(r40_resets),
+};
+
+static int r40_clk_probe(struct udevice *dev)
+{
+	struct sunxi_clk_priv *priv = dev_get_priv(dev);
+
+	priv->base = dev_read_addr_ptr(dev);
+	if (!priv->base)
+		return -ENOMEM;
+
+	priv->desc = (const struct ccu_desc *)dev_get_driver_data(dev);
+	if (!priv->desc)
+		return -EINVAL;
+
+	return 0;
+}
+
+static int r40_clk_bind(struct udevice *dev)
+{
+	return sunxi_reset_bind(dev, 80);
+}
+
+static const struct udevice_id r40_clk_ids[] = {
+	{ .compatible = "allwinner,sun8i-r40-ccu",
+	  .data = (ulong)&sun8i_r40_ccu_desc },
+	{ }
+};
+
+U_BOOT_DRIVER(clk_sun8i_r40) = {
+	.name		= "sun8i_r40_ccu",
+	.id		= UCLASS_CLK,
+	.of_match	= r40_clk_ids,
+	.priv_auto_alloc_size	= sizeof(struct sunxi_clk_priv),
+	.ops		= &sunxi_clk_ops,
+	.probe		= r40_clk_probe,
+	.bind		= r40_clk_bind,
+};