[2/3] target/riscv: optimize indirect branches

Message ID 20180809214356.27690-3-cota@braap.org
State New
Headers show
Series
  • target/riscv: use tcg_lookup_and_goto_ptr
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Commit Message

Emilio G. Cota Aug. 9, 2018, 9:43 p.m.
Signed-off-by: Emilio G. Cota <cota@braap.org>
---
 target/riscv/translate.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Richard Henderson Aug. 10, 2018, 3:06 p.m. | #1
On 08/09/2018 02:43 PM, Emilio G. Cota wrote:
> Signed-off-by: Emilio G. Cota <cota@braap.org>
> ---
>  target/riscv/translate.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index ec2988b4f6..66a80ca772 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -548,7 +548,7 @@ static void gen_jalr(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
>          if (rd != 0) {
>              tcg_gen_movi_tl(cpu_gpr[rd], ctx->pc_succ_insn);
>          }
> -        tcg_gen_exit_tb(NULL, 0);
> +        tcg_gen_lookup_and_goto_ptr();
>  
>          if (misaligned) {
>              gen_set_label(misaligned);
> 


Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

Patch

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index ec2988b4f6..66a80ca772 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -548,7 +548,7 @@  static void gen_jalr(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
         if (rd != 0) {
             tcg_gen_movi_tl(cpu_gpr[rd], ctx->pc_succ_insn);
         }
-        tcg_gen_exit_tb(NULL, 0);
+        tcg_gen_lookup_and_goto_ptr();
 
         if (misaligned) {
             gen_set_label(misaligned);