From patchwork Sat May 14 19:42:26 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Blue Swirl X-Patchwork-Id: 95583 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id B0B301007D1 for ; Sun, 15 May 2011 05:43:00 +1000 (EST) Received: from localhost ([::1]:48791 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QLKjq-0000S5-4f for incoming@patchwork.ozlabs.org; Sat, 14 May 2011 15:42:58 -0400 Received: from eggs.gnu.org ([140.186.70.92]:42063) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QLKjg-0000Rz-H3 for qemu-devel@nongnu.org; Sat, 14 May 2011 15:42:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QLKje-0003Tl-S9 for qemu-devel@nongnu.org; Sat, 14 May 2011 15:42:48 -0400 Received: from mail-qw0-f45.google.com ([209.85.216.45]:35191) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QLKje-0003Tg-Ni for qemu-devel@nongnu.org; Sat, 14 May 2011 15:42:46 -0400 Received: by qwj8 with SMTP id 8so2054079qwj.4 for ; Sat, 14 May 2011 12:42:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:from:date:message-id:subject:to :content-type; bh=h5DQm0o0Qkmat/E8bvAsdv1TF6uFn4NcBKUwc94E234=; b=E/l0MvBh3o9gcDwzPJD41cYAk6LCtafpKDfI68NqMIhWiaRWCE5DVg4eG6/j4rVfyW EbzAzgaWtXsoipL1PRtCA0ltzccc4C4sUGiLqjbeVUERb2XXBA0aMnvQ//Ho7ZjkpFva QFKjQiPjYbWwXAi3LhDRew6WFHd277cWOHcZg= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:from:date:message-id:subject:to:content-type; b=Db/ciW+ERr8dk5WXeWA2DS9t7qgXeAjdIf0bVZ8q0WhnZ5B8NrP1SF4O2nlC9YuP/u S+7Fv3J9R58tL36+3LVj32D6a6n4CoiFV2yxrpnX0ypPjo2c8WyIM+8/GeMqqGrDNS6T cRquN28G7lZdmmqYgUFzxRCamtRQjqkLNuBRk= Received: by 10.224.214.3 with SMTP id gy3mr1975385qab.387.1305402166282; Sat, 14 May 2011 12:42:46 -0700 (PDT) MIME-Version: 1.0 Received: by 10.224.54.148 with HTTP; Sat, 14 May 2011 12:42:26 -0700 (PDT) From: Blue Swirl Date: Sat, 14 May 2011 22:42:26 +0300 Message-ID: To: qemu-devel X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 209.85.216.45 Subject: [Qemu-devel] [PATCH 10/11] Add new qemu_ld and qemu_st functions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Strawman version, WIP. Signed-off-by: Blue Swirl --- tcg/i386/tcg-target.c | 6 ++++++ tcg/tcg-op.h | 49 +++++++++++++++++++++++++++++++++++++++++++++++++ tcg/tcg-opc.h | 3 +++ 3 files changed, 58 insertions(+), 0 deletions(-) DEF(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) @@ -292,6 +294,7 @@ DEF(qemu_st64, 0, 4, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) #else /* TCG_TARGET_REG_BITS == 32 */ DEF(qemu_ld8u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) +DEF(qemu_ld8u_new, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) DEF(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) DEF(qemu_ld16u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) DEF(qemu_ld16s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) From 62d19f778b533fedef35d607dcfcdc9a4ca7d52e Mon Sep 17 00:00:00 2001 Message-Id: <62d19f778b533fedef35d607dcfcdc9a4ca7d52e.1305401750.git.blauwirbel@gmail.com> In-Reply-To: <6e21df8e369388a3152dcc7da30431c672e1ee37.1305401750.git.blauwirbel@gmail.com> References: <6e21df8e369388a3152dcc7da30431c672e1ee37.1305401750.git.blauwirbel@gmail.com> From: Blue Swirl Date: Sat, 14 May 2011 17:56:35 +0000 Subject: [PATCH 10/11] Add new qemu_ld and qemu_st functions Strawman version, WIP. Signed-off-by: Blue Swirl --- tcg/i386/tcg-target.c | 6 ++++++ tcg/tcg-op.h | 49 +++++++++++++++++++++++++++++++++++++++++++++++++ tcg/tcg-opc.h | 3 +++ 3 files changed, 58 insertions(+), 0 deletions(-) diff --git a/tcg/i386/tcg-target.c b/tcg/i386/tcg-target.c index 8fc80af..b31e8bc 100644 --- a/tcg/i386/tcg-target.c +++ b/tcg/i386/tcg-target.c @@ -1676,6 +1676,9 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_qemu_st(s, args, 3, TCG_AREG0); break; #endif + case INDEX_op_qemu_ld8u_new: + tcg_out_qemu_ld(s, args, 0, args[2]); + break; #if TCG_TARGET_REG_BITS == 32 case INDEX_op_brcond2_i32: @@ -1860,6 +1863,7 @@ static const TCGTargetOpDef x86_op_defs[] = { #if TCG_TARGET_REG_BITS == 64 { INDEX_op_qemu_ld8u, { "r", "L" } }, + { INDEX_op_qemu_ld8u_new, { "r", "L", "r" } }, { INDEX_op_qemu_ld8s, { "r", "L" } }, { INDEX_op_qemu_ld16u, { "r", "L" } }, { INDEX_op_qemu_ld16s, { "r", "L" } }, @@ -1874,6 +1878,7 @@ static const TCGTargetOpDef x86_op_defs[] = { { INDEX_op_qemu_st64, { "L", "L" } }, #elif TARGET_LONG_BITS <= TCG_TARGET_REG_BITS { INDEX_op_qemu_ld8u, { "r", "L" } }, + { INDEX_op_qemu_ld8u_new, { "r", "L", "r" } }, { INDEX_op_qemu_ld8s, { "r", "L" } }, { INDEX_op_qemu_ld16u, { "r", "L" } }, { INDEX_op_qemu_ld16s, { "r", "L" } }, @@ -1886,6 +1891,7 @@ static const TCGTargetOpDef x86_op_defs[] = { { INDEX_op_qemu_st64, { "L", "L", "L" } }, #else { INDEX_op_qemu_ld8u, { "r", "L", "L" } }, + { INDEX_op_qemu_ld8u_new, { "r", "L", "L", "r" } }, { INDEX_op_qemu_ld8s, { "r", "L", "L" } }, { INDEX_op_qemu_ld16u, { "r", "L", "L" } }, { INDEX_op_qemu_ld16s, { "r", "L", "L" } }, diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index 207a89f..eb62a06 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -141,6 +141,19 @@ static inline void tcg_gen_qemu_ldst_op_i64_i32(TCGOpcode opc, TCGv_i64 val, *gen_opparam_ptr++ = mem_index; } +static inline void tcg_gen_qemu_ldst_op_new_i64_i32(TCGOpcode opc, + TCGv_i64 val, + TCGv_i32 addr, + TCGv_ptr r_cpustate, + TCGArg mem_index) +{ + *gen_opc_ptr++ = opc; + *gen_opparam_ptr++ = GET_TCGV_I64(val); + *gen_opparam_ptr++ = GET_TCGV_I32(addr); + *gen_opparam_ptr++ = GET_TCGV_PTR(r_cpustate); + *gen_opparam_ptr++ = mem_index; +} + static inline void tcg_gen_qemu_ldst_op_i64_i64(TCGOpcode opc, TCGv_i64 val, TCGv_i64 addr, TCGArg mem_index) { @@ -150,6 +163,19 @@ static inline void tcg_gen_qemu_ldst_op_i64_i64(TCGOpcode opc, TCGv_i64 val, *gen_opparam_ptr++ = mem_index; } +static inline void tcg_gen_qemu_ldst_op_new_i64_i64(TCGOpcode opc, + TCGv_i64 val, + TCGv_i64 addr, + TCGv_ptr r_cpustate, + TCGArg mem_index) +{ + *gen_opc_ptr++ = opc; + *gen_opparam_ptr++ = GET_TCGV_I64(val); + *gen_opparam_ptr++ = GET_TCGV_I64(addr); + *gen_opparam_ptr++ = GET_TCGV_PTR(r_cpustate); + *gen_opparam_ptr++ = mem_index; +} + static inline void tcg_gen_op4_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2, TCGv_i32 arg3, TCGv_i32 arg4) { @@ -2149,6 +2175,8 @@ static inline void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, #define tcg_temp_free tcg_temp_free_i32 #define tcg_gen_qemu_ldst_op tcg_gen_op3i_i32 #define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i32 +#define tcg_gen_qemu_ldst_op_new tcg_gen_op4i_i32 +#define tcg_gen_qemu_ldst_op_new_i64 tcg_gen_qemu_ldst_op_new_i64_i32 #define TCGV_UNUSED(x) TCGV_UNUSED_I32(x) #define TCGV_EQUAL(a, b) TCGV_EQUAL_I32(a, b) #else @@ -2160,6 +2188,8 @@ static inline void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, #define tcg_temp_free tcg_temp_free_i64 #define tcg_gen_qemu_ldst_op tcg_gen_op3i_i64 #define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i64 +#define tcg_gen_qemu_ldst_op_new tcg_gen_op4i_i64 +#define tcg_gen_qemu_ldst_op_new_i64 tcg_gen_qemu_ldst_op_new_i64_i64 #define TCGV_UNUSED(x) TCGV_UNUSED_I64(x) #define TCGV_EQUAL(a, b) TCGV_EQUAL_I64(a, b) #endif @@ -2198,6 +2228,18 @@ static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index) #endif } +static inline void tcg_gen_qemu_ld8u_new(TCGv ret, TCGv addr, TCGv r_cpustate, + int mem_index) +{ +#if TARGET_LONG_BITS == 32 + tcg_gen_op3i_i32(INDEX_op_qemu_ld8u_new, ret, addr, r_cpustate, mem_index); +#else + tcg_gen_op4i_i32(INDEX_op_qemu_ld8u_new, TCGV_LOW(ret), TCGV_LOW(addr), + TCGV_HIGH(addr), r_cpustate, mem_index); + tcg_gen_movi_i32(TCGV_HIGH(ret), 0); +#endif +} + static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index) { #if TARGET_LONG_BITS == 32 @@ -2314,6 +2356,13 @@ static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index) tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8u, ret, addr, mem_index); } +static inline void tcg_gen_qemu_ld8u_new(TCGv ret, TCGv addr, TCGv r_cpustate, + int mem_index) +{ + tcg_gen_qemu_ldst_op_new(INDEX_op_qemu_ld8u_new, ret, addr, r_cpustate, + mem_index); +} + static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index) { tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8s, ret, addr, mem_index); diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h index 2c7ca1a..6660529 100644 --- a/tcg/tcg-opc.h +++ b/tcg/tcg-opc.h @@ -239,8 +239,10 @@ DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) #if TCG_TARGET_REG_BITS == 32 #if TARGET_LONG_BITS == 32 DEF(qemu_ld8u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) +DEF(qemu_ld8u_new, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) #else DEF(qemu_ld8u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) +DEF(qemu_ld8u, 1, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) #endif #if TARGET_LONG_BITS == 32 DEF(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) @@ -292,6 +294,7 @@ DEF(qemu_st64, 0, 4, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) #else /* TCG_TARGET_REG_BITS == 32 */ DEF(qemu_ld8u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) +DEF(qemu_ld8u_new, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) DEF(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) DEF(qemu_ld16u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) DEF(qemu_ld16s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) -- 1.7.2.5