From patchwork Fri May 13 16:58:15 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Makarov X-Patchwork-Id: 95494 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id A62E3B6F07 for ; Sat, 14 May 2011 01:53:08 +1000 (EST) Received: (qmail 5863 invoked by alias); 13 May 2011 15:53:06 -0000 Received: (qmail 5853 invoked by uid 22791); 13 May 2011 15:53:04 -0000 X-SWARE-Spam-Status: No, hits=-6.3 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_HI, SPF_HELO_PASS, T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from mx1.redhat.com (HELO mx1.redhat.com) (209.132.183.28) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Fri, 13 May 2011 15:52:47 +0000 Received: from int-mx12.intmail.prod.int.phx2.redhat.com (int-mx12.intmail.prod.int.phx2.redhat.com [10.5.11.25]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id p4DFqkgD015071 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK) for ; Fri, 13 May 2011 11:52:47 -0400 Received: from ns3.rdu.redhat.com (ns3.rdu.redhat.com [10.11.255.199]) by int-mx12.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id p4DFqkjj016882; Fri, 13 May 2011 11:52:46 -0400 Received: from 1005.home (ovpn-113-50.phx2.redhat.com [10.3.113.50]) by ns3.rdu.redhat.com (8.13.8/8.13.8) with ESMTP id p4DFqfqd008060; Fri, 13 May 2011 11:52:45 -0400 Message-ID: <4DCD6327.2050508@redhat.com> Date: Fri, 13 May 2011 12:58:15 -0400 From: Vladimir Makarov User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.17) Gecko/20110428 Fedora/3.1.10-1.fc14 Thunderbird/3.1.10 MIME-Version: 1.0 To: gcc-patches CC: Jeff Law Subject: RFA: patch to fix PR48971 X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org The following patch solves the problem described on http://gcc.gnu.org/bugzilla/show_bug.cgi?id=48971 The patch was successfully bootstrapped on x86-64 and checked for ppc64, ia64, i686-linux, i686-apple-darwin, mips, arm, s390x, and sparc with and without -msoft-float. Is it ok to submit to the trunk? 2011-05-13 Vladimir Makarov PR rtl-optimization/48971 * ira.c (setup_pressure_classes): Don't check register move cost for classes with one registers. Don't add pressure class if there is a pressure class with the same available hard registers. Check contains_reg_of_mode. Fix a typo in collecting temp_hard_regset. Ignore hard registers not belonging to a class. Index: ira.c =================================================================== --- ira.c (revision 173706) +++ ira.c (working copy) @@ -799,27 +799,30 @@ setup_pressure_classes (void) { if (ira_available_class_regs[cl] == 0) continue; - /* Check that the moves between any hard registers of the - current class are not more expensive for a legal mode than - load/store of the hard registers of the current class. Such - class is a potential candidate to be a register pressure - class. */ - for (m = 0; m < NUM_MACHINE_MODES; m++) + if (ira_available_class_regs[cl] != 1) { - COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); - AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); - AND_COMPL_HARD_REG_SET (temp_hard_regset, - ira_prohibited_class_mode_regs[cl][m]); - if (hard_reg_set_empty_p (temp_hard_regset)) + /* Check that the moves between any hard registers of the + current class are not more expensive for a legal mode + than load/store of the hard registers of the current + class. Such class is a potential candidate to be a + register pressure class. */ + for (m = 0; m < NUM_MACHINE_MODES; m++) + { + COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); + AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); + AND_COMPL_HARD_REG_SET (temp_hard_regset, + ira_prohibited_class_mode_regs[cl][m]); + if (hard_reg_set_empty_p (temp_hard_regset)) + continue; + ira_init_register_move_cost_if_necessary ((enum machine_mode) m); + cost = ira_register_move_cost[m][cl][cl]; + if (cost <= ira_max_memory_move_cost[m][cl][1] + || cost <= ira_max_memory_move_cost[m][cl][0]) + break; + } + if (m >= NUM_MACHINE_MODES) continue; - ira_init_register_move_cost_if_necessary ((enum machine_mode) m); - cost = ira_register_move_cost[m][cl][cl]; - if (cost <= ira_max_memory_move_cost[m][cl][1] - || cost <= ira_max_memory_move_cost[m][cl][0]) - break; } - if (m >= NUM_MACHINE_MODES) - continue; curr = 0; insert_p = true; COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); @@ -848,6 +851,8 @@ setup_pressure_classes (void) && (! hard_reg_set_equal_p (temp_hard_regset2, temp_hard_regset) || cl == (int) GENERAL_REGS)) continue; + if (hard_reg_set_equal_p (temp_hard_regset2, temp_hard_regset)) + insert_p = false; pressure_classes[curr++] = (enum reg_class) cl2; } /* If the current candidate is a subset of a so far added @@ -858,23 +863,44 @@ setup_pressure_classes (void) n = curr; } #ifdef ENABLE_IRA_CHECKING - /* Check pressure classes correctness: here we check that hard - registers from all register pressure classes contains all hard - registers available for the allocation. */ - CLEAR_HARD_REG_SET (temp_hard_regset); - CLEAR_HARD_REG_SET (temp_hard_regset2); - for (cl = 0; cl < LIM_REG_CLASSES; cl++) - { - for (i = 0; i < n; i++) - if ((int) pressure_classes[i] == cl) - break; - IOR_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl]); - if (i >= n) - IOR_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); - } - AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); - AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs); - ira_assert (hard_reg_set_subset_p (temp_hard_regset2, temp_hard_regset)); + { + HARD_REG_SET ignore_hard_regs; + + /* Check pressure classes correctness: here we check that hard + registers from all register pressure classes contains all hard + registers available for the allocation. */ + CLEAR_HARD_REG_SET (temp_hard_regset); + CLEAR_HARD_REG_SET (temp_hard_regset2); + COPY_HARD_REG_SET (ignore_hard_regs, no_unit_alloc_regs); + for (cl = 0; cl < LIM_REG_CLASSES; cl++) + { + /* For some targets (like MIPS with MD_REGS), there are some + classes with hard registers available for allocation but + not able to hold value of any mode. */ + for (m = 0; m < NUM_MACHINE_MODES; m++) + if (contains_reg_of_mode[cl][m]) + break; + if (m >= NUM_MACHINE_MODES) + { + IOR_HARD_REG_SET (ignore_hard_regs, reg_class_contents[cl]); + continue; + } + for (i = 0; i < n; i++) + if ((int) pressure_classes[i] == cl) + break; + IOR_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl]); + if (i < n) + IOR_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); + } + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + /* Some targets (like SPARC with ICC reg) have alocatable regs + for which no reg class is defined. */ + if (REGNO_REG_CLASS (i) == NO_REGS) + SET_HARD_REG_BIT (ignore_hard_regs, i); + AND_COMPL_HARD_REG_SET (temp_hard_regset, ignore_hard_regs); + AND_COMPL_HARD_REG_SET (temp_hard_regset2, ignore_hard_regs); + ira_assert (hard_reg_set_subset_p (temp_hard_regset2, temp_hard_regset)); + } #endif ira_pressure_classes_num = 0; for (i = 0; i < n; i++)