From patchwork Tue Aug 7 13:59:57 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aapo Vienamo X-Patchwork-Id: 954534 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nvidia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41lGQD2mBNz9s4s for ; Wed, 8 Aug 2018 00:01:08 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389407AbeHGQOt (ORCPT ); Tue, 7 Aug 2018 12:14:49 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:8875 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389406AbeHGQOs (ORCPT ); Tue, 7 Aug 2018 12:14:48 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1, AES128-SHA) id ; Tue, 07 Aug 2018 07:00:06 -0700 Received: from HQMAIL106.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 07 Aug 2018 07:00:20 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 07 Aug 2018 07:00:20 -0700 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Tue, 7 Aug 2018 14:00:20 +0000 Received: from HQMAIL104.nvidia.com (172.18.146.11) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Tue, 7 Aug 2018 14:00:19 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1347.2 via Frontend Transport; Tue, 7 Aug 2018 14:00:19 +0000 Received: from dhcp-10-21-25-168.Nvidia.com (Not Verified[10.21.25.201]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 07 Aug 2018 07:00:19 -0700 From: Aapo Vienamo To: Ulf Hansson , Rob Herring , Mark Rutland , Thierry Reding , Jonathan Hunter , "Adrian Hunter" , Mikko Perttunen CC: , , , , Aapo Vienamo Subject: [PATCH 1/8] dt-bindings: mmc: Add DQS trim value to Tegra SDHCI Date: Tue, 7 Aug 2018 16:59:57 +0300 Message-ID: <1533650404-18125-2-git-send-email-avienamo@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1533650404-18125-1-git-send-email-avienamo@nvidia.com> References: <1533650404-18125-1-git-send-email-avienamo@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Document HS400 DQS trim value device tree property. Signed-off-by: Aapo Vienamo --- Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt index 3c7960a..7d294f3 100644 --- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt +++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt @@ -72,6 +72,7 @@ Optional properties for Tegra210 and Tegra186: trimmer value for non-tunable modes. - nvidia,default-trim : Specify the default outbound clock trimmer value. +- nvidia,dqs-trim : Specify DQS trim value for HS400 timing Notes on the pad calibration pull up and pulldown offset values: - The property values are drive codes which are programmed into the @@ -88,6 +89,8 @@ Optional properties for Tegra210 and Tegra186: - The values are programmed to the Vendor Clock Control Register. Please refer to the reference manual of the SoC for correct values. + - The DQS trim values are only used on controllers which support + HS400 timing. Example: sdhci@700b0000 {