[1/8] dt-bindings: mmc: Add DQS trim value to Tegra SDHCI

Message ID 1533650404-18125-2-git-send-email-avienamo@nvidia.com
State New
Headers show
Series
  • Tegra SDHCI support HS400 on Tegra210 and Tegra186
Related show

Commit Message

Aapo Vienamo Aug. 7, 2018, 1:59 p.m.
Document HS400 DQS trim value device tree property.

Signed-off-by: Aapo Vienamo <avienamo@nvidia.com>
---
 Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt | 3 +++
 1 file changed, 3 insertions(+)

Comments

Thierry Reding Aug. 9, 2018, 11:36 a.m. | #1
On Tue, Aug 07, 2018 at 04:59:57PM +0300, Aapo Vienamo wrote:
> Document HS400 DQS trim value device tree property.
> 
> Signed-off-by: Aapo Vienamo <avienamo@nvidia.com>
> ---
>  Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
> index 3c7960a..7d294f3 100644
> --- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
> +++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
> @@ -72,6 +72,7 @@ Optional properties for Tegra210 and Tegra186:
>    trimmer value for non-tunable modes.
>  - nvidia,default-trim : Specify the default outbound clock trimmer
>    value.
> +- nvidia,dqs-trim : Specify DQS trim value for HS400 timing
>  
>    Notes on the pad calibration pull up and pulldown offset values:
>      - The property values are drive codes which are programmed into the
> @@ -88,6 +89,8 @@ Optional properties for Tegra210 and Tegra186:
>      - The values are programmed to the Vendor Clock Control Register.
>        Please refer to the reference manual of the SoC for correct
>        values.
> +    - The DQS trim values are only used on controllers which support
> +      HS400 timing.

One of these additions says "DQS trim values", the other says "DQS trim
value". It is unclear from the above how many values there are. I think
this should be more explicit. Also, I don't see why the note about which
controllers the DQS trim value(s) applies to is in a separate paragraph.
Couldn't it be moved to the property description?

Also, I think the bindings should specify which generations of Tegra do
support HS400. Where else are people supposed to find that information?

Thierry
Aapo Vienamo Aug. 9, 2018, 11:45 a.m. | #2
On Thu, 9 Aug 2018 13:36:09 +0200
Thierry Reding <thierry.reding@gmail.com> wrote:

> On Tue, Aug 07, 2018 at 04:59:57PM +0300, Aapo Vienamo wrote:
> > Document HS400 DQS trim value device tree property.
> > 
> > Signed-off-by: Aapo Vienamo <avienamo@nvidia.com>
> > ---
> >  Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt | 3 +++
> >  1 file changed, 3 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
> > index 3c7960a..7d294f3 100644
> > --- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
> > +++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
> > @@ -72,6 +72,7 @@ Optional properties for Tegra210 and Tegra186:
> >    trimmer value for non-tunable modes.
> >  - nvidia,default-trim : Specify the default outbound clock trimmer
> >    value.
> > +- nvidia,dqs-trim : Specify DQS trim value for HS400 timing
> >  
> >    Notes on the pad calibration pull up and pulldown offset values:
> >      - The property values are drive codes which are programmed into the
> > @@ -88,6 +89,8 @@ Optional properties for Tegra210 and Tegra186:
> >      - The values are programmed to the Vendor Clock Control Register.
> >        Please refer to the reference manual of the SoC for correct
> >        values.
> > +    - The DQS trim values are only used on controllers which support
> > +      HS400 timing.  
> 
> One of these additions says "DQS trim values", the other says "DQS trim
> value". It is unclear from the above how many values there are. I think
> this should be more explicit. Also, I don't see why the note about which
> controllers the DQS trim value(s) applies to is in a separate paragraph.
> Couldn't it be moved to the property description?

It's a single value. The plural form is a mistake.

> Also, I think the bindings should specify which generations of Tegra do
> support HS400. Where else are people supposed to find that information?

This property is under the "Optional properties for Tegra210 and
Tegra186" section and it only applies for the said generations.

 -Aapo
--
To unsubscribe from this list: send the line "unsubscribe linux-tegra" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Thierry Reding Aug. 9, 2018, 1:46 p.m. | #3
On Thu, Aug 09, 2018 at 02:45:15PM +0300, Aapo Vienamo wrote:
> On Thu, 9 Aug 2018 13:36:09 +0200
> Thierry Reding <thierry.reding@gmail.com> wrote:
> 
> > On Tue, Aug 07, 2018 at 04:59:57PM +0300, Aapo Vienamo wrote:
> > > Document HS400 DQS trim value device tree property.
> > > 
> > > Signed-off-by: Aapo Vienamo <avienamo@nvidia.com>
> > > ---
> > >  Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt | 3 +++
> > >  1 file changed, 3 insertions(+)
> > > 
> > > diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
> > > index 3c7960a..7d294f3 100644
> > > --- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
> > > +++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
> > > @@ -72,6 +72,7 @@ Optional properties for Tegra210 and Tegra186:
> > >    trimmer value for non-tunable modes.
> > >  - nvidia,default-trim : Specify the default outbound clock trimmer
> > >    value.
> > > +- nvidia,dqs-trim : Specify DQS trim value for HS400 timing
> > >  
> > >    Notes on the pad calibration pull up and pulldown offset values:
> > >      - The property values are drive codes which are programmed into the
> > > @@ -88,6 +89,8 @@ Optional properties for Tegra210 and Tegra186:
> > >      - The values are programmed to the Vendor Clock Control Register.
> > >        Please refer to the reference manual of the SoC for correct
> > >        values.
> > > +    - The DQS trim values are only used on controllers which support
> > > +      HS400 timing.  
> > 
> > One of these additions says "DQS trim values", the other says "DQS trim
> > value". It is unclear from the above how many values there are. I think
> > this should be more explicit. Also, I don't see why the note about which
> > controllers the DQS trim value(s) applies to is in a separate paragraph.
> > Couldn't it be moved to the property description?
> 
> It's a single value. The plural form is a mistake.
> 
> > Also, I think the bindings should specify which generations of Tegra do
> > support HS400. Where else are people supposed to find that information?
> 
> This property is under the "Optional properties for Tegra210 and
> Tegra186" section and it only applies for the said generations.

What's the point of specifying that they are only used on controllers
which support HS400? Are you saying that only a subset of the SDHCI
controllers on Tegra210 and Tegra186 support HS400?

Thierry
Aapo Vienamo Aug. 9, 2018, 2:06 p.m. | #4
On Thu, 9 Aug 2018 15:46:48 +0200
Thierry Reding <thierry.reding@gmail.com> wrote:

> On Thu, Aug 09, 2018 at 02:45:15PM +0300, Aapo Vienamo wrote:
> > On Thu, 9 Aug 2018 13:36:09 +0200
> > Thierry Reding <thierry.reding@gmail.com> wrote:
> >   
> > > On Tue, Aug 07, 2018 at 04:59:57PM +0300, Aapo Vienamo wrote:  
> > > > Document HS400 DQS trim value device tree property.
> > > > 
> > > > Signed-off-by: Aapo Vienamo <avienamo@nvidia.com>
> > > > ---
> > > >  Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt | 3 +++
> > > >  1 file changed, 3 insertions(+)
> > > > 
> > > > diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
> > > > index 3c7960a..7d294f3 100644
> > > > --- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
> > > > +++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
> > > > @@ -72,6 +72,7 @@ Optional properties for Tegra210 and Tegra186:
> > > >    trimmer value for non-tunable modes.
> > > >  - nvidia,default-trim : Specify the default outbound clock trimmer
> > > >    value.
> > > > +- nvidia,dqs-trim : Specify DQS trim value for HS400 timing
> > > >  
> > > >    Notes on the pad calibration pull up and pulldown offset values:
> > > >      - The property values are drive codes which are programmed into the
> > > > @@ -88,6 +89,8 @@ Optional properties for Tegra210 and Tegra186:
> > > >      - The values are programmed to the Vendor Clock Control Register.
> > > >        Please refer to the reference manual of the SoC for correct
> > > >        values.
> > > > +    - The DQS trim values are only used on controllers which support
> > > > +      HS400 timing.    
> > > 
> > > One of these additions says "DQS trim values", the other says "DQS trim
> > > value". It is unclear from the above how many values there are. I think
> > > this should be more explicit. Also, I don't see why the note about which
> > > controllers the DQS trim value(s) applies to is in a separate paragraph.
> > > Couldn't it be moved to the property description?  
> > 
> > It's a single value. The plural form is a mistake.
> >   
> > > Also, I think the bindings should specify which generations of Tegra do
> > > support HS400. Where else are people supposed to find that information?  
> > 
> > This property is under the "Optional properties for Tegra210 and
> > Tegra186" section and it only applies for the said generations.  
> 
> What's the point of specifying that they are only used on controllers
> which support HS400? Are you saying that only a subset of the SDHCI
> controllers on Tegra210 and Tegra186 support HS400?

Yes, on Tegra210 and Tegra186 only SDMMC4 supports HS400.

 -Aapo
--
To unsubscribe from this list: send the line "unsubscribe linux-tegra" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Thierry Reding Aug. 9, 2018, 2:09 p.m. | #5
On Thu, Aug 09, 2018 at 05:06:04PM +0300, Aapo Vienamo wrote:
> On Thu, 9 Aug 2018 15:46:48 +0200
> Thierry Reding <thierry.reding@gmail.com> wrote:
> 
> > On Thu, Aug 09, 2018 at 02:45:15PM +0300, Aapo Vienamo wrote:
> > > On Thu, 9 Aug 2018 13:36:09 +0200
> > > Thierry Reding <thierry.reding@gmail.com> wrote:
> > >   
> > > > On Tue, Aug 07, 2018 at 04:59:57PM +0300, Aapo Vienamo wrote:  
> > > > > Document HS400 DQS trim value device tree property.
> > > > > 
> > > > > Signed-off-by: Aapo Vienamo <avienamo@nvidia.com>
> > > > > ---
> > > > >  Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt | 3 +++
> > > > >  1 file changed, 3 insertions(+)
> > > > > 
> > > > > diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
> > > > > index 3c7960a..7d294f3 100644
> > > > > --- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
> > > > > +++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
> > > > > @@ -72,6 +72,7 @@ Optional properties for Tegra210 and Tegra186:
> > > > >    trimmer value for non-tunable modes.
> > > > >  - nvidia,default-trim : Specify the default outbound clock trimmer
> > > > >    value.
> > > > > +- nvidia,dqs-trim : Specify DQS trim value for HS400 timing
> > > > >  
> > > > >    Notes on the pad calibration pull up and pulldown offset values:
> > > > >      - The property values are drive codes which are programmed into the
> > > > > @@ -88,6 +89,8 @@ Optional properties for Tegra210 and Tegra186:
> > > > >      - The values are programmed to the Vendor Clock Control Register.
> > > > >        Please refer to the reference manual of the SoC for correct
> > > > >        values.
> > > > > +    - The DQS trim values are only used on controllers which support
> > > > > +      HS400 timing.    
> > > > 
> > > > One of these additions says "DQS trim values", the other says "DQS trim
> > > > value". It is unclear from the above how many values there are. I think
> > > > this should be more explicit. Also, I don't see why the note about which
> > > > controllers the DQS trim value(s) applies to is in a separate paragraph.
> > > > Couldn't it be moved to the property description?  
> > > 
> > > It's a single value. The plural form is a mistake.
> > >   
> > > > Also, I think the bindings should specify which generations of Tegra do
> > > > support HS400. Where else are people supposed to find that information?  
> > > 
> > > This property is under the "Optional properties for Tegra210 and
> > > Tegra186" section and it only applies for the said generations.  
> > 
> > What's the point of specifying that they are only used on controllers
> > which support HS400? Are you saying that only a subset of the SDHCI
> > controllers on Tegra210 and Tegra186 support HS400?
> 
> Yes, on Tegra210 and Tegra186 only SDMMC4 supports HS400.

Good. I think that'd be good to have as part of the DT bindings
documentation.

Thierry

Patch

diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
index 3c7960a..7d294f3 100644
--- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
+++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
@@ -72,6 +72,7 @@  Optional properties for Tegra210 and Tegra186:
   trimmer value for non-tunable modes.
 - nvidia,default-trim : Specify the default outbound clock trimmer
   value.
+- nvidia,dqs-trim : Specify DQS trim value for HS400 timing
 
   Notes on the pad calibration pull up and pulldown offset values:
     - The property values are drive codes which are programmed into the
@@ -88,6 +89,8 @@  Optional properties for Tegra210 and Tegra186:
     - The values are programmed to the Vendor Clock Control Register.
       Please refer to the reference manual of the SoC for correct
       values.
+    - The DQS trim values are only used on controllers which support
+      HS400 timing.
 
 Example:
 sdhci@700b0000 {