From patchwork Tue Aug 7 07:57:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 954393 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=bp.renesas.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41l6T63G5cz9ryt for ; Tue, 7 Aug 2018 18:03:06 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726073AbeHGKQM (ORCPT ); Tue, 7 Aug 2018 06:16:12 -0400 Received: from relmlor4.renesas.com ([210.160.252.174]:3597 "EHLO relmlie3.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1725815AbeHGKQM (ORCPT ); Tue, 7 Aug 2018 06:16:12 -0400 Received: from unknown (HELO relmlir4.idc.renesas.com) ([10.200.68.154]) by relmlie3.idc.renesas.com with ESMTP; 07 Aug 2018 17:03:03 +0900 Received: from relmlii2.idc.renesas.com (relmlii2.idc.renesas.com [10.200.68.66]) by relmlir4.idc.renesas.com (Postfix) with ESMTP id 4E25D5BAF4; Tue, 7 Aug 2018 17:03:03 +0900 (JST) X-IronPort-AV: E=Sophos;i="5.51,454,1526310000"; d="scan'208";a="289064357" Received: from unknown (HELO be1yocto.ree.adwin.renesas.com) ([172.29.43.62]) by relmlii2.idc.renesas.com with ESMTP; 07 Aug 2018 17:03:01 +0900 From: Biju Das To: Linus Walleij Cc: Biju Das , linux-gpio@vger.kernel.org, Simon Horman , Geert Uytterhoeven , Chris Paterson , Fabrizio Castro , linux-renesas-soc@vger.kernel.org Subject: [PATCH v3 1/5] gpio: rcar: Add GPIO hole support Date: Tue, 7 Aug 2018 08:57:02 +0100 Message-Id: <1533628626-26503-2-git-send-email-biju.das@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1533628626-26503-1-git-send-email-biju.das@bp.renesas.com> References: <1533628626-26503-1-git-send-email-biju.das@bp.renesas.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org GPIO hole is present in RZ/G1C SoC. Valid GPIO pins on bank3 are in the range GP3_0 to GP3_16 and GP3_27 to GP3_29. The GPIO pins between GP3_17 to GP3_26 are unused. Add support for handling unused GPIO's. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven --- V1-->V2 * Added gpio-reserved-ranges support for handling unused gpios. V2-->V3 * Incorporated Geert's review comment. --- drivers/gpio/gpio-rcar.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c index 350390c..5e72b27 100644 --- a/drivers/gpio/gpio-rcar.c +++ b/drivers/gpio/gpio-rcar.c @@ -314,6 +314,9 @@ static void gpio_rcar_set_multiple(struct gpio_chip *chip, unsigned long *mask, u32 val, bankmask; bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0); + if (chip->valid_mask) + bankmask &= chip->valid_mask[0]; + if (!bankmask) return; @@ -550,6 +553,9 @@ static int gpio_rcar_resume(struct device *dev) u32 mask; for (offset = 0; offset < p->gpio_chip.ngpio; offset++) { + if (!gpiochip_line_is_valid(&p->gpio_chip, offset)) + continue; + mask = BIT(offset); /* I/O pin */ if (!(p->bank_info.iointsel & mask)) {