[v2,2/4] ARM: pxa: palmtreo: Drop docg4 specific init

Message ID 20180804205923.25298-2-boris.brezillon@bootlin.com
State New
Delegated to: Miquel Raynal
Headers show
Series
  • Untitled series #59326
Related show

Commit Message

Boris Brezillon Aug. 4, 2018, 8:59 p.m.
The docg4 driver has been removed. Remove the code that was registering
a docg4 device.

Suggested-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
---
Changes in v2:
- new patch
---
 arch/arm/mach-pxa/palmtreo.c | 31 -------------------------------
 1 file changed, 31 deletions(-)

Comments

Robert Jarzmik Aug. 19, 2018, 7:38 p.m. | #1
Boris Brezillon <boris.brezillon@bootlin.com> writes:

> The docg4 driver has been removed. Remove the code that was registering
> a docg4 device.
>
> Suggested-by: Miquel Raynal <miquel.raynal@bootlin.com>
> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
No answer for several weeks from the maintainers, so let's say they lost
interest.

Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>

Cheers.
Miquel Raynal Aug. 20, 2018, 7:46 a.m. | #2
Hi Kostya,

Kostya Porotchkin <kostap@marvell.com> wrote on Sun, 19 Aug 2018
14:12:16 +0000:

> Hi, Miguel,
> 
> We clearly have a problem with BBT on this 8K-page NAND.
> The Linux driver is unable to find BBT after reboot, even if it reports that the new table was written upon previous boot.
> It looks like the u-boot also lost the BBT information after reboot.
> So something is not yet working well with this 4GB device.
> 
> Marvell>> nand info  
> 
> Device 0: nand0, sector size 1024 KiB
>   Page size       8192 b
>   OOB size         448 b
>   Erase size   1048576 b
>   subpagesize     8192 b
>   options     0x     200
>   bbt options 0x   a0000
> Marvell>> nand bad  
> 
> Device 0 bad blocks:
>   ff800000
>   ff900000
>   ffa00000
>   ffb00000
>   ffc00000
>   ffd00000
>   ffe00000
>   fff00000

This enlarging list is very likely to show a mismatch between U-Boot
and Linux ECC configuration, you should check that first. It will
probably explain why BBT is not recognized.

Thanks,
Miquèl
Kostya Porotchkin Aug. 20, 2018, 7:50 a.m. | #3
Hi, Miguel,

I see the same issue in u-boot.
When I run "nand bad", it takes some time to scan and write the BBT, so the second call to this function returns fast (I believe the BBT is cached in DRAM).
However after reset the "nand bad" again takes time to return, so I believe the BBT was not written in previous session.

Regards
Kosta

> -----Original Message-----
> From: Miquel Raynal [mailto:miquel.raynal@bootlin.com]
> Sent: Monday, August 20, 2018 10:47
> To: Kostya Porotchkin <kostap@marvell.com>
> Cc: Daniel Mack <daniel@zonque.org>; Haojian Zhuang
> <haojian.zhuang@gmail.com>; Richard Weinberger <richard@nod.at>; linux-
> mtd@lists.infradead.org; David Woodhouse <dwmw2@infradead.org>;
> Brian Norris <computersforpeace@gmail.com>; Marek Vasut
> <marek.vasut@gmail.com>; Mike Dunn <mikedunn@newsguy.com>; Sergey
> Larin <cerg2010cerg2010@mail.ru>
> Subject: Re: [EXT] Re: nand speed test
> 
> Hi Kostya,
> 
> Kostya Porotchkin <kostap@marvell.com> wrote on Sun, 19 Aug 2018
> 14:12:16 +0000:
> 
> > Hi, Miguel,
> >
> > We clearly have a problem with BBT on this 8K-page NAND.
> > The Linux driver is unable to find BBT after reboot, even if it reports that
> the new table was written upon previous boot.
> > It looks like the u-boot also lost the BBT information after reboot.
> > So something is not yet working well with this 4GB device.
> >
> > Marvell>> nand info
> >
> > Device 0: nand0, sector size 1024 KiB
> >   Page size       8192 b
> >   OOB size         448 b
> >   Erase size   1048576 b
> >   subpagesize     8192 b
> >   options     0x     200
> >   bbt options 0x   a0000
> > Marvell>> nand bad
> >
> > Device 0 bad blocks:
> >   ff800000
> >   ff900000
> >   ffa00000
> >   ffb00000
> >   ffc00000
> >   ffd00000
> >   ffe00000
> >   fff00000
> 
> This enlarging list is very likely to show a mismatch between U-Boot and
> Linux ECC configuration, you should check that first. It will probably explain
> why BBT is not recognized.
> 
> Thanks,
> Miquèl

Patch

diff --git a/arch/arm/mach-pxa/palmtreo.c b/arch/arm/mach-pxa/palmtreo.c
index 4cc05ecce618..b66b0b11d717 100644
--- a/arch/arm/mach-pxa/palmtreo.c
+++ b/arch/arm/mach-pxa/palmtreo.c
@@ -403,36 +403,6 @@  static void __init palmtreo_leds_init(void)
 	platform_device_register(&palmtreo_leds);
 }
 
-/******************************************************************************
- * diskonchip docg4 flash
- ******************************************************************************/
-#if defined(CONFIG_MACH_TREO680)
-/* REVISIT: does the centro have this device also? */
-#if IS_ENABLED(CONFIG_MTD_NAND_DOCG4)
-static struct resource docg4_resources[] = {
-	{
-		.start	= 0x00000000,
-		.end	= 0x00001FFF,
-		.flags	= IORESOURCE_MEM,
-	},
-};
-
-static struct platform_device treo680_docg4_flash = {
-	.name   = "docg4",
-	.id     = -1,
-	.resource = docg4_resources,
-	.num_resources = ARRAY_SIZE(docg4_resources),
-};
-
-static void __init treo680_docg4_flash_init(void)
-{
-	platform_device_register(&treo680_docg4_flash);
-}
-#else
-static inline void treo680_docg4_flash_init(void) {}
-#endif
-#endif
-
 /******************************************************************************
  * Machine init
  ******************************************************************************/
@@ -517,7 +487,6 @@  static void __init treo680_init(void)
 	treo680_gpio_init();
 	palm27x_mmc_init(GPIO_NR_TREO_SD_DETECT_N, GPIO_NR_TREO680_SD_READONLY,
 			GPIO_NR_TREO680_SD_POWER, 0);
-	treo680_docg4_flash_init();
 }
 #endif