[1/2,SRU,Bionic] ACPICA: iasl: Add SMMUv3 device ID mapping index support

Message ID 20180803165225.7277-2-dann.frazier@canonical.com
State New
Headers show
Series
  • Support MSI control interrupts for SMMUv3
Related show

Commit Message

dann frazier Aug. 3, 2018, 4:52 p.m.
From: Hanjun Guo <hanjun.guo@linaro.org>

BugLink: https://bugs.launchpad.net/bugs/1785282

ACPICA commit 5c371879e035122c5807752f42247fd091d107d6

SMMUv3 device ID mapping index is used for SMMUv3
MSI which is introduced in IORT spec revision c,
add its support for iasl.

Tested with iasl -t IORT then get the right SMMUv3
node in iort.asl.

Link: https://github.com/acpica/acpica/commit/5c371879
Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
Signed-off-by: Bob Moore <robert.moore@intel.com>
Signed-off-by: Erik Schmauss <erik.schmauss@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
(cherry picked from commit 4c106aa411ee7c1919589f283a4f17888dfee387)
Signed-off-by: dann frazier <dann.frazier@canonical.com>
---
 include/acpi/actbl2.h | 1 +
 1 file changed, 1 insertion(+)

Patch

diff --git a/include/acpi/actbl2.h b/include/acpi/actbl2.h
index 686b6f8c09dc7..d90277eb24547 100644
--- a/include/acpi/actbl2.h
+++ b/include/acpi/actbl2.h
@@ -810,6 +810,7 @@  struct acpi_iort_smmu_v3 {
 	u8 pxm;
 	u8 reserved1;
 	u16 reserved2;
+	u32 id_mapping_index;
 };
 
 /* Values for Model field above */