| Message ID | 20180802141012.19970-3-andrea.merello@gmail.com |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | None | expand |
On Thu, Aug 02, 2018 at 04:10:08PM +0200, Andrea Merello wrote: > The width of the "length register" cannot be autodetected, and it is now > specified with a DT property. Add DOC for it. > > Cc: Rob Herring <robh+dt@kernel.org> > Cc: Mark Rutland <mark.rutland@arm.com> > Cc: devicetree@vger.kernel.org > Cc: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> > Signed-off-by: Andrea Merello <andrea.merello@gmail.com> > Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> > --- > Changes in v2: > - change property name > - property is now optional > - cc DT maintainer > Changes in v3: > - reword > - cc DT maintainerS and ML > Changes in v4: > - specify the unit, the valid range and the default value > --- > Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt > index a2b8bfaec43c..aec4a41a03ae 100644 > --- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt > +++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt > @@ -41,6 +41,10 @@ Optional properties: > - xlnx,include-sg: Tells configured for Scatter-mode in > the hardware. > Optional properties for AXI DMA: > +- xlnx,sg-length-width: Should be set to the width in bits of the length > + register as configured in h/w. Takes values {8...26}. If the property > + is missing or invalid then the default value 23 is used. This is the > + maximum value that is supported by all IP versions. If 23 is the max, then why is the range 8-26? -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Tue, Aug 7, 2018 at 4:56 PM, Rob Herring <robh@kernel.org> wrote: > On Thu, Aug 02, 2018 at 04:10:08PM +0200, Andrea Merello wrote: >> The width of the "length register" cannot be autodetected, and it is now >> specified with a DT property. Add DOC for it. >> >> Cc: Rob Herring <robh+dt@kernel.org> >> Cc: Mark Rutland <mark.rutland@arm.com> >> Cc: devicetree@vger.kernel.org >> Cc: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> >> Signed-off-by: Andrea Merello <andrea.merello@gmail.com> >> Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> >> --- >> Changes in v2: >> - change property name >> - property is now optional >> - cc DT maintainer >> Changes in v3: >> - reword >> - cc DT maintainerS and ML >> Changes in v4: >> - specify the unit, the valid range and the default value >> --- >> Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt | 4 ++++ >> 1 file changed, 4 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt >> index a2b8bfaec43c..aec4a41a03ae 100644 >> --- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt >> +++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt >> @@ -41,6 +41,10 @@ Optional properties: >> - xlnx,include-sg: Tells configured for Scatter-mode in >> the hardware. >> Optional properties for AXI DMA: >> +- xlnx,sg-length-width: Should be set to the width in bits of the length >> + register as configured in h/w. Takes values {8...26}. If the property >> + is missing or invalid then the default value 23 is used. This is the >> + maximum value that is supported by all IP versions. > > If 23 is the max, then why is the range 8-26? 26 In the max possible value and it is supported by some HW IP flavours. 23 is the max value supported by ALL HW IP flavours -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 02-08-18, 16:10, Andrea Merello wrote: > The width of the "length register" cannot be autodetected, and it is now > specified with a DT property. Add DOC for it. Add Documentation for it... > > Cc: Rob Herring <robh+dt@kernel.org> > Cc: Mark Rutland <mark.rutland@arm.com> > Cc: devicetree@vger.kernel.org > Cc: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> > Signed-off-by: Andrea Merello <andrea.merello@gmail.com> > Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> > --- > Changes in v2: > - change property name > - property is now optional > - cc DT maintainer > Changes in v3: > - reword > - cc DT maintainerS and ML > Changes in v4: > - specify the unit, the valid range and the default value > --- > Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt > index a2b8bfaec43c..aec4a41a03ae 100644 > --- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt > +++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt > @@ -41,6 +41,10 @@ Optional properties: > - xlnx,include-sg: Tells configured for Scatter-mode in > the hardware. > Optional properties for AXI DMA: > +- xlnx,sg-length-width: Should be set to the width in bits of the length > + register as configured in h/w. Takes values {8...26}. If the property > + is missing or invalid then the default value 23 is used. This is the > + maximum value that is supported by all IP versions. > - xlnx,mcdma: Tells whether configured for multi-channel mode in the hardware. > Optional properties for VDMA: > - xlnx,flush-fsync: Tells which channel to Flush on Frame sync. > -- > 2.17.1
On Mon, Aug 27, 2018 at 7:31 AM Vinod <vkoul@kernel.org> wrote: > > On 02-08-18, 16:10, Andrea Merello wrote: > > The width of the "length register" cannot be autodetected, and it is now > > specified with a DT property. Add DOC for it. > > Add Documentation for it... OK > > > > Cc: Rob Herring <robh+dt@kernel.org> > > Cc: Mark Rutland <mark.rutland@arm.com> > > Cc: devicetree@vger.kernel.org > > Cc: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> > > Signed-off-by: Andrea Merello <andrea.merello@gmail.com> > > Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> > > --- > > Changes in v2: > > - change property name > > - property is now optional > > - cc DT maintainer > > Changes in v3: > > - reword > > - cc DT maintainerS and ML > > Changes in v4: > > - specify the unit, the valid range and the default value > > --- > > Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt | 4 ++++ > > 1 file changed, 4 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt > > index a2b8bfaec43c..aec4a41a03ae 100644 > > --- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt > > +++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt > > @@ -41,6 +41,10 @@ Optional properties: > > - xlnx,include-sg: Tells configured for Scatter-mode in > > the hardware. > > Optional properties for AXI DMA: > > +- xlnx,sg-length-width: Should be set to the width in bits of the length > > + register as configured in h/w. Takes values {8...26}. If the property > > + is missing or invalid then the default value 23 is used. This is the > > + maximum value that is supported by all IP versions. > > - xlnx,mcdma: Tells whether configured for multi-channel mode in the hardware. > > Optional properties for VDMA: > > - xlnx,flush-fsync: Tells which channel to Flush on Frame sync. > > -- > > 2.17.1 > > -- > ~Vinod
diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt index a2b8bfaec43c..aec4a41a03ae 100644 --- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt +++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt @@ -41,6 +41,10 @@ Optional properties: - xlnx,include-sg: Tells configured for Scatter-mode in the hardware. Optional properties for AXI DMA: +- xlnx,sg-length-width: Should be set to the width in bits of the length + register as configured in h/w. Takes values {8...26}. If the property + is missing or invalid then the default value 23 is used. This is the + maximum value that is supported by all IP versions. - xlnx,mcdma: Tells whether configured for multi-channel mode in the hardware. Optional properties for VDMA: - xlnx,flush-fsync: Tells which channel to Flush on Frame sync.