From patchwork Wed Aug 1 16:32:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aapo Vienamo X-Patchwork-Id: 952271 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nvidia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41gf7Q4Ckxz9ryn for ; Thu, 2 Aug 2018 02:35:46 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2403809AbeHASUb (ORCPT ); Wed, 1 Aug 2018 14:20:31 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:4686 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2403800AbeHASUb (ORCPT ); Wed, 1 Aug 2018 14:20:31 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1, AES128-SHA) id ; Wed, 01 Aug 2018 09:33:45 -0700 Received: from HQMAIL107.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Wed, 01 Aug 2018 09:33:58 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Wed, 01 Aug 2018 09:33:58 -0700 Received: from HQMAIL104.nvidia.com (172.18.146.11) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Wed, 1 Aug 2018 16:33:58 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1347.2 via Frontend Transport; Wed, 1 Aug 2018 16:33:57 +0000 Received: from dhcp-10-21-25-168.Nvidia.com (Not Verified[10.21.25.201]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Wed, 01 Aug 2018 09:33:58 -0700 From: Aapo Vienamo To: Rob Herring , Mark Rutland , Thierry Reding , Jonathan Hunter , Ulf Hansson , Adrian Hunter , Mikko Perttunen , Stefan Agner CC: , , , , Aapo Vienamo Subject: [PATCH 25/40] mmc: sdhci: Add a quirk to disable card clock during tuning Date: Wed, 1 Aug 2018 19:32:15 +0300 Message-ID: <1533141150-10511-26-git-send-email-avienamo@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1533141150-10511-1-git-send-email-avienamo@nvidia.com> References: <1533141150-10511-1-git-send-email-avienamo@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Add a quirk to disable card clock when the tuning command is sent. This has to be done to prevent the SDHCI controller from hanging on Tegra210. Without the quirk enabled there appears to be around 10% chance that the tuning sequence will fail and time out due to the controller locking up. Signed-off-by: Aapo Vienamo --- drivers/mmc/host/sdhci.c | 15 +++++++++++++++ drivers/mmc/host/sdhci.h | 2 ++ 2 files changed, 17 insertions(+) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 04dc443..166b16f 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -2175,6 +2175,7 @@ static void sdhci_send_tuning(struct sdhci_host *host, u32 opcode) struct mmc_request mrq = {}; unsigned long flags; u32 b = host->sdma_boundary; + u16 clk; spin_lock_irqsave(&host->lock, flags); @@ -2183,6 +2184,13 @@ static void sdhci_send_tuning(struct sdhci_host *host, u32 opcode) cmd.mrq = &mrq; mrq.cmd = &cmd; + + if (host->quirks2 & SDHCI_QUIRK2_TUNE_DIS_CARD_CLK) { + clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); + clk &= ~SDHCI_CLOCK_CARD_EN; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + } + /* * In response to CMD19, the card sends 64 bytes of tuning * block to the Host Controller. So we set the block size @@ -2213,6 +2221,13 @@ static void sdhci_send_tuning(struct sdhci_host *host, u32 opcode) mmiowb(); spin_unlock_irqrestore(&host->lock, flags); + if (host->quirks2 & SDHCI_QUIRK2_TUNE_DIS_CARD_CLK) { + udelay(1); + clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); + clk |= SDHCI_CLOCK_CARD_EN; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + } + /* Wait for Buffer Read Ready interrupt */ wait_event_timeout(host->buf_ready_int, (host->tuning_done == 1), msecs_to_jiffies(50)); diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 0a99008..cc411b0 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -452,6 +452,8 @@ struct sdhci_host { #define SDHCI_QUIRK2_DISABLE_HW_TIMEOUT (1<<17) /* Don't clear the SDHCI_TRANSFER_MODE register on tuning commands */ #define SDHCI_QUIRK2_TUNE_SKIP_XFERMODE_REG_PROG (1<<18) +/* Disable card clock during tuning */ +#define SDHCI_QUIRK2_TUNE_DIS_CARD_CLK (1<<19) int irq; /* Device IRQ */ void __iomem *ioaddr; /* Mapped address */