From patchwork Wed Aug 1 11:12:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Florian Eckert X-Patchwork-Id: 952087 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=dev.tdt.de Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41gW6v4T7bz9s3x for ; Wed, 1 Aug 2018 21:19:51 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387715AbeHANFG (ORCPT ); Wed, 1 Aug 2018 09:05:06 -0400 Received: from ms.tdt.de ([195.243.126.94]:46112 "EHLO mail.dev.tdt.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S2387590AbeHANFG (ORCPT ); Wed, 1 Aug 2018 09:05:06 -0400 X-Greylist: delayed 419 seconds by postgrey-1.27 at vger.kernel.org; Wed, 01 Aug 2018 09:05:05 EDT Received: from feckert01.dev.tdt.de (unknown [10.2.3.40]) by mail.dev.tdt.de (Postfix) with ESMTPSA id C35502011F; Wed, 1 Aug 2018 11:12:48 +0000 (UTC) From: Florian Eckert To: linux-gpio@vger.kernel.org Cc: linus.walleij@linaro.org, linux-kernel@vger.kernel.org, fe@dev.tdt.de Subject: [PATCH] gpio: Add driver for PC Engines APU2/APU3 GPIOs Date: Wed, 1 Aug 2018 13:12:43 +0200 Message-Id: <20180801111243.2848-1-fe@dev.tdt.de> X-Mailer: git-send-email 2.11.0 X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.dev.tdt.de Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add a new device driver "gpio-apu" which will now handle the GPIOs on APU2 and APU3 devices from PC Engines. - APU2/APU3 -> front button reset support - APU3 -> SIM switch support Signed-off-by: Florian Eckert --- drivers/gpio/Kconfig | 10 ++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio-apu.c | 344 ++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 355 insertions(+) create mode 100644 drivers/gpio/gpio-apu.c diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 71c0ab46f216..9eb8977ba2e5 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -117,6 +117,16 @@ config GPIO_AMDPT driver for GPIO functionality on Promontory IOHub Require ACPI ASL code to enumerate as a platform device. +config GPIO_APU + tristate "PC Engines APU2/APU3 GPIO support" + depends on X86 + select GPIO_GENERIC + help + Say Y here to support GPIO functionality on APU2/APU3 boards + from PC Engines. + - APU2/APU3 -> front button reset support + - APU3 -> SIM switch support + config GPIO_ASPEED tristate "Aspeed GPIO support" depends on (ARCH_ASPEED || COMPILE_TEST) && OF_GPIO diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 1324c8f966a7..feea4effcf29 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_GPIO_ALTERA) += gpio-altera.o obj-$(CONFIG_GPIO_ALTERA_A10SR) += gpio-altera-a10sr.o obj-$(CONFIG_GPIO_AMD8111) += gpio-amd8111.o obj-$(CONFIG_GPIO_AMDPT) += gpio-amdpt.o +obj-$(CONFIG_GPIO_APU) += gpio-apu.o obj-$(CONFIG_GPIO_ARIZONA) += gpio-arizona.o obj-$(CONFIG_GPIO_ATH79) += gpio-ath79.o obj-$(CONFIG_GPIO_ASPEED) += gpio-aspeed.o diff --git a/drivers/gpio/gpio-apu.c b/drivers/gpio/gpio-apu.c new file mode 100644 index 000000000000..18171c13917a --- /dev/null +++ b/drivers/gpio/gpio-apu.c @@ -0,0 +1,344 @@ +/* PC Engines APU2/APU3 GPIO device driver + * + * Copyright (C) 2018 Florian Eckert + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version + * + * This program is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define DEVNAME "gpio-apu" + +#define APU_FCH_ACPI_MMIO_BASE 0xFED80000 +#define APU_FCH_GPIO_BASE (APU_FCH_ACPI_MMIO_BASE + 0x1500) +#define APU_GPIO_BIT_WRITE 22 +#define APU_GPIO_BIT_READ 16 +#define APU_GPIO_BIT_DIR 23 +#define APU_IOSIZE sizeof(u32) + +#define APU2_NUM_GPIO 1 +#define APU3_NUM_GPIO 2 + +struct apu_gpio_pdata { + struct platform_device *pdev; + struct gpio_chip *chip; + unsigned long *offset; + void __iomem **addr; + int iosize; /* for devm_ioremap() */ + spinlock_t lock; +}; + +static struct apu_gpio_pdata *apu_gpio; +static struct platform_device *keydev; + +/* APU2 */ +static unsigned long apu2_gpio_offset[APU2_NUM_GPIO] = { + APU_FCH_GPIO_BASE + 89 * APU_IOSIZE, //KEY +}; +static void __iomem *apu2_gpio_addr[APU2_NUM_GPIO] = {NULL}; + +/* APU3 */ +static unsigned long apu3_gpio_offset[APU3_NUM_GPIO] = { + APU_FCH_GPIO_BASE + 89 * APU_IOSIZE, //KEY + APU_FCH_GPIO_BASE + 90 * APU_IOSIZE, //SIM +}; +static void __iomem *apu3_gpio_addr[APU3_NUM_GPIO] = {NULL, NULL}; + +static int gpio_apu_get_dir (struct gpio_chip *chip, unsigned offset) +{ + u32 val; + + spin_lock(&apu_gpio->lock); + + val = ~ioread32(apu_gpio->addr[offset]); + val = (val >> APU_GPIO_BIT_DIR) & 1; + + spin_unlock(&apu_gpio->lock); + + return val; +} + +static int gpio_apu_dir_in (struct gpio_chip *chip, unsigned offset) +{ + u32 val; + + spin_lock(&apu_gpio->lock); + + val = ioread32(apu_gpio->addr[offset]); + val &= ~BIT(APU_GPIO_BIT_DIR); + iowrite32(val, apu_gpio->addr[offset]); + + spin_unlock(&apu_gpio->lock); + + return 0; +} + +static int gpio_apu_dir_out (struct gpio_chip *chip, unsigned offset, + int value) +{ + u32 val; + + spin_lock(&apu_gpio->lock); + + val = ioread32(apu_gpio->addr[offset]); + val |= BIT(APU_GPIO_BIT_DIR); + iowrite32(val, apu_gpio->addr[offset]); + + spin_unlock(&apu_gpio->lock); + + return 0; +} + +static int gpio_apu_get_data (struct gpio_chip *chip, unsigned offset) +{ + u32 val; + + spin_lock(&apu_gpio->lock); + + val = ioread32(apu_gpio->addr[offset]); + val = (val >> APU_GPIO_BIT_READ) & 1; + + spin_unlock(&apu_gpio->lock); + + return val; +} + +static void gpio_apu_set_data (struct gpio_chip *chip, unsigned offset, int value) +{ + u32 val; + + spin_lock(&apu_gpio->lock); + + val = ioread32(apu_gpio->addr[offset]); + if (value) + val |= BIT(APU_GPIO_BIT_WRITE); + else + val &= ~BIT(APU_GPIO_BIT_WRITE); + iowrite32(val, apu_gpio->addr[offset]); + + spin_unlock(&apu_gpio->lock); +} + +static const struct dmi_system_id apu_gpio_dmi_table[] __initconst = { + /* PC Engines APU2 with "Legacy" bios < 4.0.8 */ + { + .ident = "apu2", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"), + DMI_MATCH(DMI_BOARD_NAME, "APU2") + } + }, + /* PC Engines APU2 with "Legacy" bios >= 4.0.8 */ + { + .ident = "apu2", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"), + DMI_MATCH(DMI_BOARD_NAME, "apu2") + } + }, + /* PC Engines APU2 with "Mainline" bios */ + { + .ident = "apu2", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"), + DMI_MATCH(DMI_BOARD_NAME, "PC Engines apu2") + } + }, + /* PC Engines APU3 with "Legancy" bios >= 4.0.7 */ + { + .ident = "apu2", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"), + DMI_MATCH(DMI_BOARD_NAME, "APU3") + } + }, + {} +}; +MODULE_DEVICE_TABLE(dmi, apu_gpio_dmi_table); + +static struct gpio_chip gpio_apu_chip = { + .label = "gpio-apu", + .owner = THIS_MODULE, + .base = -1, + .get_direction = gpio_apu_get_dir, + .direction_input = gpio_apu_dir_in, + .direction_output = gpio_apu_dir_out, + .get = gpio_apu_get_data, + .set = gpio_apu_set_data, +}; + +static struct gpio_keys_button apu_gpio_keys[] = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = 60, + .gpio = 510, + .active_low = 1, + }, +}; + +static void register_gpio_keys_polled(int id, unsigned poll_interval, + unsigned nbuttons, + struct gpio_keys_button *buttons) +{ + struct gpio_keys_platform_data pdata = { }; + int err; + + keydev = platform_device_alloc("gpio-keys-polled", id); + if (!keydev) { + printk(KERN_ERR "Failed to allocate gpio-keys platform device\n"); + return; + } + + pdata.poll_interval = poll_interval; + pdata.nbuttons = nbuttons; + pdata.buttons = buttons; + + err = platform_device_add_data(keydev, &pdata, sizeof(pdata)); + if (err) { + dev_err(&keydev->dev, "failed to add platform data to key driver (%d)", err); + goto err_put_pdev; + } + + err = platform_device_add(keydev); + if (err) { + dev_err(&keydev->dev, "failed to register key platform device (%d)", err); + goto err_put_pdev; + } + + return; + +err_put_pdev: + platform_device_put(keydev); + keydev = NULL; +} + +static int __init apu_gpio_probe(struct platform_device *pdev) +{ + int i; + int ret; + + apu_gpio = devm_kzalloc(&pdev->dev, sizeof(*apu_gpio), GFP_KERNEL); + + if (!apu_gpio) + return -ENOMEM; + + apu_gpio->pdev = pdev; + apu_gpio->chip = &gpio_apu_chip; + spin_lock_init(&apu_gpio->lock); + + if (dmi_match(DMI_PRODUCT_NAME, "APU3")) { + apu_gpio->offset = apu3_gpio_offset; + apu_gpio->addr = apu3_gpio_addr; + apu_gpio->iosize = APU_IOSIZE; + apu_gpio->chip->ngpio = ARRAY_SIZE(apu3_gpio_offset); + for( i = 0; i < ARRAY_SIZE(apu3_gpio_offset); i++) { + apu3_gpio_addr[i] = devm_ioremap(&pdev->dev, + apu_gpio->offset[i], apu_gpio->iosize); + if (!apu3_gpio_addr[i]) { + return -ENOMEM; + } + } + } else if (dmi_match(DMI_BOARD_NAME, "APU2") || + dmi_match(DMI_BOARD_NAME, "apu2") || + dmi_match(DMI_BOARD_NAME, "PC Engines apu2")) { + apu_gpio->offset = apu2_gpio_offset; + apu_gpio->addr = apu2_gpio_addr; + apu_gpio->iosize = APU_IOSIZE; + apu_gpio->chip->ngpio = ARRAY_SIZE(apu2_gpio_offset); + for( i = 0; i < ARRAY_SIZE(apu2_gpio_offset); i++) { + apu2_gpio_addr[i] = devm_ioremap(&pdev->dev, + apu_gpio->offset[i], apu_gpio->iosize); + if (!apu2_gpio_addr[i]) { + return -ENOMEM; + } + } + } + + ret = gpiochip_add(&gpio_apu_chip); + if (ret) { + pr_err("Adding gpiochip failed\n"); + } + + register_gpio_keys_polled(-1, 20, ARRAY_SIZE(apu_gpio_keys), apu_gpio_keys); + + return ret; +} + +static struct platform_driver apu_gpio_driver = { + .driver = { + .name = KBUILD_MODNAME, + }, +}; + +static int __init apu_gpio_init(void) +{ + struct platform_device *pdev; + int err; + + if (!dmi_match(DMI_SYS_VENDOR, "PC Engines")) { + pr_err("No PC Engines board detected\n"); + return -ENODEV; + } + if (!(dmi_match(DMI_PRODUCT_NAME, "APU") || + dmi_match(DMI_PRODUCT_NAME, "APU2") || + dmi_match(DMI_PRODUCT_NAME, "APU3") || + dmi_match(DMI_PRODUCT_NAME, "apu2") || + dmi_match(DMI_PRODUCT_NAME, "PC Engines apu2"))) { + pr_err("Unknown PC Engines board: %s\n", + dmi_get_system_info(DMI_PRODUCT_NAME)); + return -ENODEV; + } + + pdev = platform_device_register_simple(KBUILD_MODNAME, -1, NULL, 0); + if (IS_ERR(pdev)) { + pr_err("Device allocation failed\n"); + return PTR_ERR(pdev); + } + + err = platform_driver_probe(&apu_gpio_driver, apu_gpio_probe); + if (err) { + pr_err("Probe platform driver failed\n"); + platform_device_unregister(pdev); + } + + pr_info ("%s: APU2/3 GPIO driver module loaded\n", DEVNAME); + + return err; +} + +static void __exit apu_gpio_exit(void) +{ + platform_device_unregister(keydev); + gpiochip_remove(apu_gpio->chip); + platform_device_unregister(apu_gpio->pdev); + platform_driver_unregister(&apu_gpio_driver); + pr_info ("%s: APU2/3 GPIO driver module unloaded\n", DEVNAME); +} + +module_init(apu_gpio_init); +module_exit(apu_gpio_exit); + +MODULE_AUTHOR("Florian Eckert "); +MODULE_DESCRIPTION("PC Engines APU2/APU3 family GPIO driver"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:gpio_apu");