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[3/5] PCI: cadence: Check whether MSI is masked before sending it

Message ID 1532971373-8591-1-git-send-email-adouglas@cadence.com
State Changes Requested
Delegated to: Lorenzo Pieralisi
Headers show
Series Add MSI-X support for cadence EP driver | expand

Commit Message

Alan Douglas July 30, 2018, 5:22 p.m. UTC 
The EP driver did not check the mask bit for each MSI before
sending it in raise_irq.  This is now checked, and EINVAL is
returned if masked.

Signed-off-by: Alan Douglas <adouglas@cadence.com>
---
 drivers/pci/controller/pcie-cadence-ep.c |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)
diff mbox series

Patch

diff --git a/drivers/pci/controller/pcie-cadence-ep.c b/drivers/pci/controller/pcie-cadence-ep.c
index c3a0889..db75280 100644
--- a/drivers/pci/controller/pcie-cadence-ep.c
+++ b/drivers/pci/controller/pcie-cadence-ep.c
@@ -332,6 +332,11 @@  static int cdns_pcie_ep_send_msi_irq(struct cdns_pcie_ep *ep, u8 fn,
 	if (!interrupt_num || interrupt_num > msi_count)
 		return -EINVAL;
 
+	/* Check whether MSI is masked */
+	data = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_MASK_64);
+	if (data & (1<<(interrupt_num-1)))
+		return -EINVAL;
+
 	/* Compute the data value to be written. */
 	data_mask = msi_count - 1;
 	data = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_DATA_64);