[2/5] PCI: cadence: Write MSI data with 32bits

Message ID 1532971358-8220-1-git-send-email-adouglas@cadence.com
State Changes Requested
Delegated to: Lorenzo Pieralisi
Headers show
Series
  • Add MSI-X support for cadence EP driver
Related show

Commit Message

Alan Douglas July 30, 2018, 5:22 p.m.
According to the PCIe specification, although the MSI data is only
16bits, the upper 16bits should be written as 0.  Use writel
instead of writew when writing the MSI data to the host.

Signed-off-by: Alan Douglas <adouglas@cadence.com>
---
 drivers/pci/controller/pcie-cadence-ep.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

Patch

diff --git a/drivers/pci/controller/pcie-cadence-ep.c b/drivers/pci/controller/pcie-cadence-ep.c
index 6692654..c3a0889 100644
--- a/drivers/pci/controller/pcie-cadence-ep.c
+++ b/drivers/pci/controller/pcie-cadence-ep.c
@@ -355,7 +355,7 @@  static int cdns_pcie_ep_send_msi_irq(struct cdns_pcie_ep *ep, u8 fn,
 		ep->irq_pci_addr = (pci_addr & ~pci_addr_mask);
 		ep->irq_pci_fn = fn;
 	}
-	writew(data, ep->irq_cpu_addr + (pci_addr & pci_addr_mask));
+	writel(data, ep->irq_cpu_addr + (pci_addr & pci_addr_mask));
 
 	return 0;
 }