@@ -15,6 +15,7 @@
#include <miiphy.h>
#include <net.h>
#include <netdev.h>
+#include <phy.h>
#include "fec_mxc.h"
#include <asm/io.h>
@@ -46,7 +47,7 @@ DECLARE_GLOBAL_DATA_PTR;
#endif
#ifndef CONFIG_FEC_XCV_TYPE
-#define CONFIG_FEC_XCV_TYPE MII100
+#define CONFIG_FEC_XCV_TYPE PHY_INTERFACE_MODE_MII100
#endif
/*
@@ -397,11 +398,11 @@ static void fec_reg_setup(struct fec_priv *fec)
/* Start with frame length = 1518, common for all modes. */
rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT;
- if (fec->xcv_type != SEVENWIRE) /* xMII modes */
+ if (fec->xcv_type != PHY_INTERFACE_MODE_SEVENWIRE) /* xMII modes */
rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE;
- if (fec->xcv_type == RGMII)
+ if (fec->xcv_type == PHY_INTERFACE_MODE_RGMII)
rcntrl |= FEC_RCNTRL_RGMII;
- else if (fec->xcv_type == RMII)
+ else if (fec->xcv_type == PHY_INTERFACE_MODE_RMII)
rcntrl |= FEC_RCNTRL_RMII;
writel(rcntrl, &fec->eth->r_cntrl);
@@ -552,7 +553,7 @@ static int fec_init(struct eth_device *dev, bd_t *bd)
fec_reg_setup(fec);
- if (fec->xcv_type != SEVENWIRE)
+ if (fec->xcv_type != PHY_INTERFACE_MODE_SEVENWIRE)
fec_mii_setspeed(fec->bus->priv);
/* Set Opcode/Pause Duration Register */
@@ -583,7 +584,7 @@ static int fec_init(struct eth_device *dev, bd_t *bd)
writel((uint32_t)addr, &fec->eth->erdsr);
#ifndef CONFIG_PHYLIB
- if (fec->xcv_type != SEVENWIRE)
+ if (fec->xcv_type != PHY_INTERFACE_MODE_SEVENWIRE)
miiphy_restart_aneg(dev);
#endif
fec_open(dev);
@@ -1233,7 +1234,7 @@ static int fec_phy_init(struct fec_priv *priv, struct udevice *dev)
mask = 1 << CONFIG_FEC_MXC_PHYADDR;
#endif
- phydev = phy_find_by_mask(priv->bus, mask, priv->interface);
+ phydev = phy_find_by_mask(priv->bus, mask, priv->xcv_type);
if (!phydev)
return -ENODEV;
@@ -1283,8 +1284,7 @@ static int fecmxc_probe(struct udevice *dev)
}
priv->bus = bus;
- priv->xcv_type = CONFIG_FEC_XCV_TYPE;
- priv->interface = pdata->phy_interface;
+ priv->xcv_type = pdata->phy_interface;
ret = fec_phy_init(priv, dev);
if (ret)
goto err_phy;
@@ -223,19 +223,10 @@ struct fec_bd {
uint32_t data_pointer; /* payload's buffer address */
};
-/* Supported phy types on this platform */
-enum xceiver_type {
- SEVENWIRE, /* 7-wire */
- MII10, /* MII 10Mbps */
- MII100, /* MII 100Mbps */
- RMII, /* RMII */
- RGMII, /* RGMII */
-};
-
/* @brief i.MX27-FEC private structure */
struct fec_priv {
struct ethernet_regs *eth; /* pointer to register'S base */
- enum xceiver_type xcv_type; /* transceiver type */
+ phy_interface_t xcv_type; /* transceiver type */
struct fec_bd *rbd_base; /* RBD ring */
int rbd_index; /* next receive BD to read */
struct fec_bd *tbd_base; /* TBD ring */
@@ -250,10 +241,6 @@ struct fec_priv {
int phy_id;
int (*mii_postcall)(int);
#endif
-
-#ifdef CONFIG_DM_ETH
- u32 interface;
-#endif
};
void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
@@ -56,7 +56,7 @@
/* Networking Configs */
#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_FEC_XCV_TYPE PHY_INTERFACE_MODE_RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 4
#define CONFIG_PHY_ATHEROS
@@ -69,7 +69,7 @@
/* Network */
#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_FEC_XCV_TYPE PHY_INTERFACE_MODE_RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 6
#define CONFIG_IP_DEFRAG
@@ -19,7 +19,7 @@
#define CONFIG_MXC_UART_BASE UART5_BASE
#define CONSOLE_DEV "ttymxc4"
-#define CONFIG_FEC_XCV_TYPE RMII
+#define CONFIG_FEC_XCV_TYPE PHY_INTERFACE_MODE_RMII
#define CONFIG_SF_DEFAULT_BUS 3
#define CONFIG_SF_DEFAULT_CS 0
@@ -18,7 +18,7 @@
#define CONFIG_MXC_UART_BASE UART2_BASE
#define CONSOLE_DEV "ttymxc1"
-#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_FEC_XCV_TYPE PHY_INTERFACE_MODE_RGMII
#define CONFIG_SF_DEFAULT_BUS 3
#define CONFIG_SF_DEFAULT_CS 1
@@ -18,7 +18,7 @@
#define CONFIG_MXC_UART_BASE UART2_BASE
#define CONSOLE_DEV "ttymxc1"
-#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_FEC_XCV_TYPE PHY_INTERFACE_MODE_RGMII
#define CONFIG_SF_DEFAULT_BUS 0
#define CONFIG_SF_DEFAULT_CS 0
@@ -83,7 +83,7 @@
/* Ethernet */
#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_FEC_XCV_TYPE PHY_INTERFACE_MODE_RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 6
#define CONFIG_PHY_ATHEROS
@@ -24,7 +24,7 @@
#define CONFIG_CSF_SIZE 0x4000
/* Network */
-#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_FEC_XCV_TYPE PHY_INTERFACE_MODE_RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 0
@@ -178,7 +178,7 @@
/* Ethernet */
#define CONFIG_FEC_MXC_PHYADDR 0
-#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_FEC_XCV_TYPE PHY_INTERFACE_MODE_RGMII
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_PHY_ATHEROS
#define CONFIG_ETHPRIME "FEC0"
@@ -57,7 +57,7 @@
/* Network */
#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE RMII
+#define CONFIG_FEC_XCV_TYPE PHY_INTERFACE_MODE_RMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 1
#define CONFIG_IP_DEFRAG
@@ -20,7 +20,7 @@
#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
/* Network */
-#define CONFIG_FEC_XCV_TYPE RMII
+#define CONFIG_FEC_XCV_TYPE PHY_INTERFACE_MODE_RMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 0
@@ -50,7 +50,7 @@
#define CONFIG_SYS_FSL_ESDHC_NUM 1
#define IMX_FEC_BASE ENET1_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE RMII
+#define CONFIG_FEC_XCV_TYPE PHY_INTERFACE_MODE_RMII
#define CONFIG_FEC_MXC_PHYADDR 0
#define CONFIG_IPADDR 192.168.10.2
@@ -43,7 +43,7 @@
/* FEC ethernet */
#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE RMII
+#define CONFIG_FEC_XCV_TYPE PHY_INTERFACE_MODE_RMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 0
#define CONFIG_ARP_TIMEOUT 200UL
@@ -83,7 +83,7 @@
/* Ethernet */
#ifdef CONFIG_FEC_MXC
#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_FEC_XCV_TYPE PHY_INTERFACE_MODE_RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 0
#endif
@@ -42,7 +42,7 @@
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_FEC_XCV_TYPE PHY_INTERFACE_MODE_RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 4
@@ -65,7 +65,7 @@
/* Networking Configs */
#ifdef CONFIG_NET
#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_FEC_XCV_TYPE PHY_INTERFACE_MODE_RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 4
#define CONFIG_PHY_ATHEROS
@@ -124,7 +124,7 @@
/* Ethernet support */
#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_FEC_XCV_TYPE PHY_INTERFACE_MODE_RGMII
#define CONFIG_FEC_MXC_PHYADDR 0
#define CONFIG_ARP_TIMEOUT 200UL
@@ -161,10 +161,8 @@
#ifdef CONFIG_FEC_MXC
# ifdef CONFIG_TARGET_MX6Q_ICORE_RQS
# define CONFIG_FEC_MXC_PHYADDR 3
-# define CONFIG_FEC_XCV_TYPE RGMII
# else
# define CONFIG_FEC_MXC_PHYADDR 0
-# define CONFIG_FEC_XCV_TYPE RMII
# endif
#endif
@@ -22,7 +22,6 @@
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* Dev kit SD card */
/* Ethernet Configs */
-#define CONFIG_FEC_XCV_TYPE RMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 0
@@ -26,7 +26,7 @@
/* FEC ethernet */
#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_FEC_XCV_TYPE PHY_INTERFACE_MODE_RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 0
#define CONFIG_ARP_TIMEOUT 200UL
@@ -144,7 +144,7 @@
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0x0
-#define CONFIG_FEC_XCV_TYPE RMII
+#define CONFIG_FEC_XCV_TYPE PHY_INTERFACE_MODE_RMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_PHY_SMSC
@@ -87,7 +87,7 @@
/* Ethernet Configuration */
#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_FEC_XCV_TYPE PHY_INTERFACE_MODE_RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 1
@@ -29,7 +29,7 @@
/* Ethernet Configuration */
#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_FEC_XCV_TYPE PHY_INTERFACE_MODE_RGMII
#define CONFIG_FEC_MXC_PHYADDR 0
#define CONFIG_PHY_ATHEROS
@@ -21,7 +21,7 @@
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_FEC_XCV_TYPE PHY_INTERFACE_MODE_RGMII
#define CONFIG_FEC_MXC_PHYADDR 0
#define CONFIG_EXTRA_ENV_SETTINGS \
@@ -21,7 +21,7 @@
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_FEC_XCV_TYPE PHY_INTERFACE_MODE_RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 1
@@ -33,7 +33,7 @@
#define CONFIG_SYS_I2C_SPEED 100000
#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE RMII
+#define CONFIG_FEC_XCV_TYPE PHY_INTERFACE_MODE_RMII
#define CONFIG_FEC_MXC_PHYADDR 0
#define CONFIG_PHY_SMSC
@@ -129,7 +129,7 @@
#define IMX_FEC_BASE ENET2_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0x0
-#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_FEC_XCV_TYPE PHY_INTERFACE_MODE_RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_PHY_ATHEROS
@@ -153,7 +153,7 @@
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0x1
-#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_FEC_XCV_TYPE PHY_INTERFACE_MODE_RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_PHY_ATHEROS
@@ -189,11 +189,11 @@
#if (CONFIG_FEC_ENET_DEV == 0)
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0x2
-#define CONFIG_FEC_XCV_TYPE RMII
+#define CONFIG_FEC_XCV_TYPE PHY_INTERFACE_MODE_RMII
#elif (CONFIG_FEC_ENET_DEV == 1)
#define IMX_FEC_BASE ENET2_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0x1
-#define CONFIG_FEC_XCV_TYPE RMII
+#define CONFIG_FEC_XCV_TYPE PHY_INTERFACE_MODE_RMII
#endif
#define CONFIG_ETHPRIME "FEC"
#endif
@@ -19,7 +19,7 @@
#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
/* Network */
-#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_FEC_XCV_TYPE PHY_INTERFACE_MODE_RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 0
@@ -115,7 +115,7 @@
#define CONFIG_ETHPRIME "FEC0"
#endif
#ifndef CONFIG_FEC_XCV_TYPE
-#define CONFIG_FEC_XCV_TYPE RMII
+#define CONFIG_FEC_XCV_TYPE PHY_INTERFACE_MODE_RMII
#endif
#endif
@@ -54,7 +54,7 @@
#endif
#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_FEC_XCV_TYPE PHY_INTERFACE_MODE_RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 6
@@ -62,7 +62,7 @@
/* Ethernet Configuration */
#ifdef CONFIG_CMD_NET
#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_FEC_XCV_TYPE PHY_INTERFACE_MODE_RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 0x7
#define CONFIG_ARP_TIMEOUT 200UL
@@ -49,7 +49,7 @@
#ifdef CONFIG_FEC_MXC
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0x1
-#define CONFIG_FEC_XCV_TYPE RMII
+#define CONFIG_FEC_XCV_TYPE PHY_INTERFACE_MODE_RMII
#define CONFIG_ETHPRIME "FEC"
#endif
@@ -69,7 +69,7 @@
#endif
#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE MII100
+#define CONFIG_FEC_XCV_TYPE PHY_INTERFACE_MODE_MII100
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 0x5
#define CONFIG_PHY_SMSC
@@ -42,7 +42,7 @@
/*#define CONFIG_ESDHC_DETECT_USE_EXTERN_IRQ1*/
#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE RMII
+#define CONFIG_FEC_XCV_TYPE PHY_INTERFACE_MODE_RMII
#define CONFIG_FEC_MXC_PHYADDR 0
/* QSPI Configs*/
@@ -32,7 +32,7 @@
/* Ethernet */
#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_FEC_XCV_TYPE PHY_INTERFACE_MODE_RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 3
@@ -30,7 +30,7 @@
/* Ethernet */
#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_FEC_XCV_TYPE PHY_INTERFACE_MODE_RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 3
@@ -17,7 +17,7 @@
#define IMX_FEC_BASE ENET2_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0x1
-#define CONFIG_FEC_XCV_TYPE RMII
+#define CONFIG_FEC_XCV_TYPE PHY_INTERFACE_MODE_RMII
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M) /* Increase due to DFU */
@@ -18,7 +18,7 @@
#define CONFIG_MXC_UART_BASE UART5_IPS_BASE_ADDR
/* Network */
-#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_FEC_XCV_TYPE PHY_INTERFACE_MODE_RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 1
@@ -12,7 +12,7 @@
#include <configs/platinum.h>
-#define CONFIG_FEC_XCV_TYPE RMII
+#define CONFIG_FEC_XCV_TYPE PHY_INTERFACE_MODE_RMII
#define CONFIG_FEC_MXC_PHYADDR 0
#define CONFIG_HOSTNAME "picon"
@@ -15,7 +15,7 @@
#include <configs/platinum.h>
-#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_FEC_XCV_TYPE PHY_INTERFACE_MODE_RGMII
#define CONFIG_FEC_MXC_PHYADDR 4
#define CONFIG_PHY_RESET_DELAY 1000
@@ -27,7 +27,7 @@
/* Ethernet Configuration */
#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_FEC_XCV_TYPE PHY_INTERFACE_MODE_RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 6
@@ -22,7 +22,7 @@
/* Ethernet */
#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_FEC_XCV_TYPE PHY_INTERFACE_MODE_RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 0x01
@@ -50,7 +50,7 @@
/* Ethernet */
#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_FEC_XCV_TYPE PHY_INTERFACE_MODE_RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 4
#define CONFIG_PHY_ATHEROS
@@ -40,7 +40,7 @@
#define CONFIG_SYS_FSL_USDHC_NUM 1
#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_FEC_XCV_TYPE PHY_INTERFACE_MODE_RGMII
#define CONFIG_FEC_MXC_PHYADDR 4
/* USB Configs */
@@ -9,7 +9,7 @@
#ifndef __CONFIG_TQMA6_MBA6_H
#define __CONFIG_TQMA6_MBA6_H
-#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_FEC_XCV_TYPE PHY_INTERFACE_MODE_RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 0x03
@@ -7,7 +7,7 @@
#define __CONFIG_TQMA6_WRU4_H
/* Ethernet */
-#define CONFIG_FEC_XCV_TYPE RMII
+#define CONFIG_FEC_XCV_TYPE PHY_INTERFACE_MODE_RMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 0x01
#define CONFIG_PHY_SMSC
@@ -33,7 +33,7 @@
/* Network support */
#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_FEC_XCV_TYPE PHY_INTERFACE_MODE_RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 6
@@ -99,7 +99,7 @@
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0x0
-#define CONFIG_FEC_XCV_TYPE RMII
+#define CONFIG_FEC_XCV_TYPE PHY_INTERFACE_MODE_RMII
#define CONFIG_ETHPRIME "FEC0"
#endif /* __CONFIG_H */
@@ -45,7 +45,7 @@
#define CONFIG_SYS_FSL_ESDHC_NUM 1
#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE RMII
+#define CONFIG_FEC_XCV_TYPE PHY_INTERFACE_MODE_RMII
#define CONFIG_FEC_MXC_PHYADDR 0
/* QSPI Configs*/
@@ -65,7 +65,7 @@
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0x0
-#define CONFIG_FEC_XCV_TYPE RMII
+#define CONFIG_FEC_XCV_TYPE PHY_INTERFACE_MODE_RMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_PHY_ATHEROS
@@ -57,7 +57,7 @@
/* Ethernet Configuration */
#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_FEC_XCV_TYPE PHY_INTERFACE_MODE_RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 1
#define CONFIG_PHY_ATHEROS
@@ -68,7 +68,7 @@
#define CONFIG_FEC_ENET_DEV 0
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0x0
-#define CONFIG_FEC_XCV_TYPE RMII
+#define CONFIG_FEC_XCV_TYPE PHY_INTERFACE_MODE_RMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_PHY_SMSC
@@ -18,7 +18,7 @@
/* Ethernet */
#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE MII100
+#define CONFIG_FEC_XCV_TYPE PHY_INTERFACE_MODE_MII100
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 0
#define CONFIG_MV88E6352_SWITCH
@@ -19,7 +19,7 @@
/* Ethernet */
#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_FEC_XCV_TYPE PHY_INTERFACE_MODE_RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 0x10
#define CONFIG_FEC_FIXED_SPEED 1000 /* No autoneg, fix Gb */
@@ -50,6 +50,7 @@
typedef enum {
PHY_INTERFACE_MODE_MII,
+ PHY_INTERFACE_MODE_MII100,
PHY_INTERFACE_MODE_GMII,
PHY_INTERFACE_MODE_SGMII,
PHY_INTERFACE_MODE_SGMII_2500,
@@ -65,6 +66,7 @@ typedef enum {
PHY_INTERFACE_MODE_XAUI,
PHY_INTERFACE_MODE_RXAUI,
PHY_INTERFACE_MODE_SFI,
+ PHY_INTERFACE_MODE_SEVENWIRE,
PHY_INTERFACE_MODE_INTERNAL,
PHY_INTERFACE_MODE_NONE, /* Must be last */
@@ -73,6 +75,7 @@ typedef enum {
static const char *phy_interface_strings[] = {
[PHY_INTERFACE_MODE_MII] = "mii",
+ [PHY_INTERFACE_MODE_MII100] = "mii100",
[PHY_INTERFACE_MODE_GMII] = "gmii",
[PHY_INTERFACE_MODE_SGMII] = "sgmii",
[PHY_INTERFACE_MODE_SGMII_2500] = "sgmii-2500",
@@ -88,6 +91,7 @@ static const char *phy_interface_strings[] = {
[PHY_INTERFACE_MODE_XAUI] = "xaui",
[PHY_INTERFACE_MODE_RXAUI] = "rxaui",
[PHY_INTERFACE_MODE_SFI] = "sfi",
+ [PHY_INTERFACE_MODE_SEVENWIRE] = "sevenwire",
[PHY_INTERFACE_MODE_INTERNAL] = "internal",
[PHY_INTERFACE_MODE_NONE] = "",
};
Use existing PHY_INTERFACE_MODE_ for xcv_type, this eventually - remove CONFIG_FEC_XCV_TYPE in DM_ETH boards since the phy interface is grabbing from DT phy-mode. - prefix PHY_INTERFACE_MODE_ for CONFIG_FEC_XCV_TYPE in non DM_ETH boards - added MII100, SEVENWIRE PHY mode Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> --- drivers/net/fec_mxc.c | 18 +++++++++--------- drivers/net/fec_mxc.h | 15 +-------------- include/configs/advantech_dms-ba16.h | 2 +- include/configs/apalis_imx6.h | 2 +- include/configs/aristainetos.h | 2 +- include/configs/aristainetos2.h | 2 +- include/configs/aristainetos2b.h | 2 +- include/configs/cgtqmx6eval.h | 2 +- include/configs/cl-som-imx7.h | 2 +- include/configs/cm_fx6.h | 2 +- include/configs/colibri_imx6.h | 2 +- include/configs/colibri_imx7.h | 2 +- include/configs/colibri_vf.h | 2 +- include/configs/dh_imx6.h | 2 +- include/configs/display5.h | 2 +- include/configs/embestmx6boards.h | 2 +- include/configs/ge_bx50v3.h | 2 +- include/configs/gw_ventana.h | 2 +- include/configs/imx6-engicam.h | 2 -- include/configs/imx6_logic.h | 1 - include/configs/kp_imx6q_tpc.h | 2 +- include/configs/liteboard.h | 2 +- include/configs/mccmon6.h | 2 +- include/configs/mx6cuboxi.h | 2 +- include/configs/mx6qarm2.h | 2 +- include/configs/mx6sabre_common.h | 2 +- include/configs/mx6slevk.h | 2 +- include/configs/mx6sxsabreauto.h | 2 +- include/configs/mx6sxsabresd.h | 2 +- include/configs/mx6ul_14x14_evk.h | 4 ++-- include/configs/mx7dsabresd.h | 2 +- include/configs/mxs.h | 2 +- include/configs/nitrogen6x.h | 2 +- include/configs/novena.h | 2 +- include/configs/opos6uldev.h | 2 +- include/configs/ot1200.h | 2 +- include/configs/pcm052.h | 2 +- include/configs/pcm058.h | 2 +- include/configs/pfla02.h | 2 +- include/configs/pico-imx6ul.h | 2 +- include/configs/pico-imx7d.h | 2 +- include/configs/platinum_picon.h | 2 +- include/configs/platinum_titanium.h | 2 +- include/configs/secomx6quq7.h | 2 +- include/configs/sksimx6.h | 2 +- include/configs/tbs2910.h | 2 +- include/configs/titanium.h | 2 +- include/configs/tqma6_mba6.h | 2 +- include/configs/tqma6_wru4.h | 2 +- include/configs/udoo.h | 2 +- include/configs/udoo_neo.h | 2 +- include/configs/vf610twr.h | 2 +- include/configs/vining_2000.h | 2 +- include/configs/wandboard.h | 2 +- include/configs/xpress.h | 2 +- include/configs/zc5202.h | 2 +- include/configs/zc5601.h | 2 +- include/phy.h | 4 ++++ 58 files changed, 68 insertions(+), 80 deletions(-)