From patchwork Fri Jul 27 21:09:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Brandt X-Patchwork-Id: 950350 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=renesas.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41chRn6PSxz9s1x for ; Sat, 28 Jul 2018 07:09:41 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389723AbeG0WdU (ORCPT ); Fri, 27 Jul 2018 18:33:20 -0400 Received: from relmlor3.renesas.com ([210.160.252.173]:26738 "EHLO relmlie2.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S2389211AbeG0WdU (ORCPT ); Fri, 27 Jul 2018 18:33:20 -0400 Received: from unknown (HELO relmlir2.idc.renesas.com) ([10.200.68.152]) by relmlie2.idc.renesas.com with ESMTP; 28 Jul 2018 06:09:38 +0900 Received: from relmlii2.idc.renesas.com (relmlii2.idc.renesas.com [10.200.68.66]) by relmlir2.idc.renesas.com (Postfix) with ESMTP id B4FB04DDC9; Sat, 28 Jul 2018 06:09:38 +0900 (JST) X-IronPort-AV: E=Sophos;i="5.51,411,1526310000"; d="scan'208";a="288098554" Received: from unknown (HELO rtamta01.rta.renesas.com) ([143.103.48.75]) by relmlii2.idc.renesas.com with ESMTP; 28 Jul 2018 06:09:36 +0900 Received: from ubuntu.localdomain (unknown [143.103.58.70]) by rtamta01.rta.renesas.com (Postfix) with ESMTP id 64CB71D9; Fri, 27 Jul 2018 21:09:31 +0000 (UTC) From: Chris Brandt To: Greg Kroah-Hartman , Rob Herring , Mark Rutland , Geert Uytterhoeven Cc: linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Simon Horman , Chris Brandt Subject: [PATCH 1/4] serial: sh-sci: Improve interrupts description Date: Fri, 27 Jul 2018 16:09:13 -0500 Message-Id: <20180727210916.66642-2-chris.brandt@renesas.com> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20180727210916.66642-1-chris.brandt@renesas.com> References: <20180727210916.66642-1-chris.brandt@renesas.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Describe interrupts property in more detail, especially when there are more than one interrupt. Signed-off-by: Chris Brandt Reviewed-by: Geert Uytterhoeven --- .../devicetree/bindings/serial/renesas,sci-serial.txt | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt index a7cda6550100..eaca9da79d83 100644 --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt @@ -73,7 +73,21 @@ Required properties: family-specific and/or generic versions. - reg: Base address and length of the I/O registers used by the UART. - - interrupts: Must contain an interrupt-specifier for the SCIx interrupt. + - interrupts: Must contain one or more interrupt-specifiers for the SCIx. + If a single interrupt is expressed, then all events are + multiplexed into this single interrupt. + + If multiple interrupts are provided by the hardware, the order + in which the interrupts are listed must match order below. Note + that some HW interrupt events may be muxed together resulting + in duplicate entries. + The interrupt order is as follows: + 1. Error (ERI) + 2. Receive buffer full (RXI) + 3. Transmit buffer empty (TXI) + 4. Break (BRI) + 5. Data Ready (DRI) + 6. Transmit End (TEI) - clocks: Must contain a phandle and clock-specifier pair for each entry in clock-names.