diff mbox series

[v1,4/4] target/riscv: set mtval and stval support

Message ID 7fc5c46c407bccc9089d7f705bdc8caaea2b67b0.1532559484.git.alistair.francis@wdc.com
State New
Headers show
Series RISC-V: Populate mtval and stval | expand

Commit Message

Alistair Francis July 25, 2018, 11:04 p.m. UTC 
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 4 ++++
 1 file changed, 4 insertions(+)
diff mbox series

Patch

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d630e8fd6c..b33950a2d4 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -133,6 +133,8 @@  static void rv32gcsu_priv1_10_0_cpu_init(Object *obj)
     set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_10_0);
     set_resetvec(env, DEFAULT_RSTVEC);
     set_feature(env, RISCV_FEATURE_MMU);
+    set_feature(env, RISCV_FEATURE_MTVAL_INST);
+    set_feature(env, RISCV_FEATURE_STVAL_INST);
 }
 
 static void rv32imacu_nommu_cpu_init(Object *obj)
@@ -161,6 +163,8 @@  static void rv64gcsu_priv1_10_0_cpu_init(Object *obj)
     set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_10_0);
     set_resetvec(env, DEFAULT_RSTVEC);
     set_feature(env, RISCV_FEATURE_MMU);
+    set_feature(env, RISCV_FEATURE_MTVAL_INST);
+    set_feature(env, RISCV_FEATURE_STVAL_INST);
 }
 
 static void rv64imacu_nommu_cpu_init(Object *obj)