From patchwork Wed Jul 25 14:38:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Brandt X-Patchwork-Id: 949256 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=renesas.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41bHtS1YJKz9rxx for ; Thu, 26 Jul 2018 00:39:28 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729847AbeGYPvZ (ORCPT ); Wed, 25 Jul 2018 11:51:25 -0400 Received: from relmlor4.renesas.com ([210.160.252.174]:38867 "EHLO relmlie3.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728631AbeGYPvZ (ORCPT ); Wed, 25 Jul 2018 11:51:25 -0400 Received: from unknown (HELO relmlir3.idc.renesas.com) ([10.200.68.153]) by relmlie3.idc.renesas.com with ESMTP; 25 Jul 2018 23:39:23 +0900 Received: from relmlii1.idc.renesas.com (relmlii1.idc.renesas.com [10.200.68.65]) by relmlir3.idc.renesas.com (Postfix) with ESMTP id 939B686898; Wed, 25 Jul 2018 23:39:23 +0900 (JST) X-IronPort-AV: E=Sophos;i="5.51,401,1526310000"; d="scan'208";a="286362017" Received: from unknown (HELO rtamta01.rta.renesas.com) ([143.103.48.75]) by relmlii1.idc.renesas.com with ESMTP; 25 Jul 2018 23:39:22 +0900 Received: from ubuntu.localdomain (unknown [143.103.58.206]) by rtamta01.rta.renesas.com (Postfix) with ESMTP id EDF691FC; Wed, 25 Jul 2018 14:39:15 +0000 (UTC) From: Chris Brandt To: Greg Kroah-Hartman , Rob Herring , Mark Rutland , Geert Uytterhoeven Cc: linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Simon Horman , Chris Brandt Subject: [PATCH v2 3/3] serial: sh-sci: Document r7s9210 bindings Date: Wed, 25 Jul 2018 09:38:50 -0500 Message-Id: <20180725143850.32985-4-chris.brandt@renesas.com> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20180725143850.32985-1-chris.brandt@renesas.com> References: <20180725143850.32985-1-chris.brandt@renesas.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add R7S9210 (RZ/A2) support. Also describe interrupts property in more detail. Signed-off-by: Chris Brandt Reviewed-by: Geert Uytterhoeven Reviewed-by: Rob Herring --- v2: * Add more details to interrupts property * Geert gave a Reviewed-by for V1, but then later said that was a mistake because it was missing the interrupts description, so I didn't include his Reviewed-by yet. --- .../devicetree/bindings/serial/renesas,sci-serial.txt | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt index 106808b55b6d..5d0997a04697 100644 --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt @@ -5,6 +5,7 @@ Required properties: - compatible: Must contain one or more of the following: - "renesas,scif-r7s72100" for R7S72100 (RZ/A1H) SCIF compatible UART. + - "renesas,scif-r7s9210" for R7S9210 (RZ/A2) SCIF compatible UART. - "renesas,scifa-r8a73a4" for R8A73A4 (R-Mobile APE6) SCIFA compatible UART. - "renesas,scifb-r8a73a4" for R8A73A4 (R-Mobile APE6) SCIFB compatible UART. - "renesas,scifa-r8a7740" for R8A7740 (R-Mobile A1) SCIFA compatible UART. @@ -72,7 +73,21 @@ Required properties: family-specific and/or generic versions. - reg: Base address and length of the I/O registers used by the UART. - - interrupts: Must contain an interrupt-specifier for the SCIx interrupt. + - interrupts: Must contain one or more interrupt-specifiers for the SCIx. + If a single interrupt is expressed, then all events are + multiplexed into this single interrupt. + + If multiple interrupts are provided by the hardware, the order + in which the interrupts are listed must match order below. Note + that some HW interrupt events may be muxed together resulting + in duplicate entires. + The interrupt order is as follows: + 1. Error (ERI) + 2. Receive buffer full (RXI) + 3. Transmit buffer empty (TXI) + 4. Break (BRI) + 5. Data Ready (DRI) + 6. Transmit End (TEI) - clocks: Must contain a phandle and clock-specifier pair for each entry in clock-names.