[v2,3/3] serial: sh-sci: Document r7s9210 bindings
diff mbox series

Message ID 20180725143850.32985-4-chris.brandt@renesas.com
State Not Applicable
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Series
  • serial: sh-sci: Add support for RZ/A2
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Commit Message

Chris Brandt July 25, 2018, 2:38 p.m. UTC
Add R7S9210 (RZ/A2) support.
Also describe interrupts property in more detail.

Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
---
v2:
 * Add more details to interrupts property
 * Geert gave a Reviewed-by for V1, but then later said that was a
   mistake because it was missing the interrupts description, so
   I didn't include his Reviewed-by yet.
---
 .../devicetree/bindings/serial/renesas,sci-serial.txt   | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)

Comments

Geert Uytterhoeven July 26, 2018, 11:41 a.m. UTC | #1
Hi Chris,

On Wed, Jul 25, 2018 at 4:39 PM Chris Brandt <chris.brandt@renesas.com> wrote:
> Add R7S9210 (RZ/A2) support.
> Also describe interrupts property in more detail.
>
> Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
> ---
> v2:
>  * Add more details to interrupts property
>  * Geert gave a Reviewed-by for V1, but then later said that was a
>    mistake because it was missing the interrupts description, so
>    I didn't include his Reviewed-by yet.

Thanks for the update!

With the below typo fixed:
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

> --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
> +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
> @@ -72,7 +73,21 @@ Required properties:
>      family-specific and/or generic versions.
>
>    - reg: Base address and length of the I/O registers used by the UART.
> -  - interrupts: Must contain an interrupt-specifier for the SCIx interrupt.
> +  - interrupts: Must contain one or more interrupt-specifiers for the SCIx.
> +                If a single interrupt is expressed, then all events are
> +                multiplexed into this single interrupt.
> +
> +                If multiple interrupts are provided by the hardware, the order
> +                in which the interrupts are listed must match order below. Note
> +                that some HW interrupt events may be muxed together resulting
> +                in duplicate entires.

entries

> +                The interrupt order is as follows:
> +                  1. Error (ERI)
> +                  2. Receive buffer full (RXI)
> +                  3. Transmit buffer empty (TXI)
> +                  4. Break (BRI)
> +                  5. Data Ready (DRI)
> +                  6. Transmit End (TEI)
>
>    - clocks: Must contain a phandle and clock-specifier pair for each entry
>      in clock-names.

Gr{oetje,eeting}s,

                        Geert
Chris Brandt July 26, 2018, 12:18 p.m. UTC | #2
Hi Geert,

On Thursday, July 26, 2018, Geert Uytterhoeven wrote:
> With the below typo fixed:
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

OK, I will fix the typo and resend.

Thank you.

Chris
Rob Herring July 30, 2018, 11:19 p.m. UTC | #3
On Wed, Jul 25, 2018 at 09:38:50AM -0500, Chris Brandt wrote:
> Add R7S9210 (RZ/A2) support.
> Also describe interrupts property in more detail.
> 
> Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
> ---
> v2:
>  * Add more details to interrupts property
>  * Geert gave a Reviewed-by for V1, but then later said that was a
>    mistake because it was missing the interrupts description, so
>    I didn't include his Reviewed-by yet.
> ---
>  .../devicetree/bindings/serial/renesas,sci-serial.txt   | 17 ++++++++++++++++-
>  1 file changed, 16 insertions(+), 1 deletion(-)

Reviewed-by: Rob Herring <robh@kernel.org>
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Patch
diff mbox series

diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
index 106808b55b6d..5d0997a04697 100644
--- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
+++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
@@ -5,6 +5,7 @@  Required properties:
   - compatible: Must contain one or more of the following:
 
     - "renesas,scif-r7s72100" for R7S72100 (RZ/A1H) SCIF compatible UART.
+    - "renesas,scif-r7s9210" for R7S9210 (RZ/A2) SCIF compatible UART.
     - "renesas,scifa-r8a73a4" for R8A73A4 (R-Mobile APE6) SCIFA compatible UART.
     - "renesas,scifb-r8a73a4" for R8A73A4 (R-Mobile APE6) SCIFB compatible UART.
     - "renesas,scifa-r8a7740" for R8A7740 (R-Mobile A1) SCIFA compatible UART.
@@ -72,7 +73,21 @@  Required properties:
     family-specific and/or generic versions.
 
   - reg: Base address and length of the I/O registers used by the UART.
-  - interrupts: Must contain an interrupt-specifier for the SCIx interrupt.
+  - interrupts: Must contain one or more interrupt-specifiers for the SCIx.
+                If a single interrupt is expressed, then all events are
+                multiplexed into this single interrupt.
+
+                If multiple interrupts are provided by the hardware, the order
+                in which the interrupts are listed must match order below. Note
+                that some HW interrupt events may be muxed together resulting
+                in duplicate entires.
+                The interrupt order is as follows:
+                  1. Error (ERI)
+                  2. Receive buffer full (RXI)
+                  3. Transmit buffer empty (TXI)
+                  4. Break (BRI)
+                  5. Data Ready (DRI)
+                  6. Transmit End (TEI)
 
   - clocks: Must contain a phandle and clock-specifier pair for each entry
     in clock-names.