From patchwork Mon May 9 21:34:16 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 94857 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 373B6B6F12 for ; Tue, 10 May 2011 07:35:40 +1000 (EST) Received: from localhost ([::1]:51925 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QJY77-0003HB-BC for incoming@patchwork.ozlabs.org; Mon, 09 May 2011 17:35:37 -0400 Received: from eggs.gnu.org ([140.186.70.92]:38239) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QJY6W-0003Dz-4X for qemu-devel@nongnu.org; Mon, 09 May 2011 17:35:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QJY6V-0006An-BF for qemu-devel@nongnu.org; Mon, 09 May 2011 17:35:00 -0400 Received: from mail-iw0-f173.google.com ([209.85.214.173]:38418) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QJY6V-0006Af-7R for qemu-devel@nongnu.org; Mon, 09 May 2011 17:34:59 -0400 Received: by iwl42 with SMTP id 42so5560360iwl.4 for ; Mon, 09 May 2011 14:34:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:sender:from:to:subject:date:message-id:x-mailer :in-reply-to:references; bh=OO61Vltf75QAMzHI9ncsWUkY/a65rMHtO4sd+YSOWy0=; b=mHmaOQgxrbvOxiZYYx86WEPbpYxX0AuiYIq1JF9hNJ4zInWr9lQqSKBm05IbusnwYg Xo7CXXrnONh7KNnO8gUTvzFoRgYY8dYAO/43vwHhru6S3ElBF7Qop9ddIMVmKtP9l4bB L+qGaEX2BhgQhJZD0uoVLFYRhqVS7B5kqiqvA= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:message-id:x-mailer:in-reply-to :references; b=Q15NlToSR7pbWvpdzeZhlCK//dEi+CvzHdcWHwCkCRl7uNmmUbG+KXCqRFa5r+5yiF WuPj31Ys0zWitSyX7EadMLng+W/wciO/pjmhNa3O4jWp4JVyvbZwmNaX87sOlXcJ25pA sUXW+PSXijFgNThq2uqbpBQquKGfJIywU9R7k= Received: by 10.43.58.148 with SMTP id wk20mr1917662icb.242.1304976898626; Mon, 09 May 2011 14:34:58 -0700 (PDT) Received: from localhost.localdomain (are.twiddle.net [75.101.38.216]) by mx.google.com with ESMTPS id ui7sm2549819icb.14.2011.05.09.14.34.57 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 09 May 2011 14:34:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 9 May 2011 14:34:16 -0700 Message-Id: <1304976889-29675-3-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.4.4 In-Reply-To: <1304976889-29675-1-git-send-email-rth@twiddle.net> References: <1304976889-29675-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 209.85.214.173 Subject: [Qemu-devel] [PATCH 02/35] target-alpha: Disassemble EV6 PALcode instructions. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The QEMU emulation PALcode will use EV6 PALcode insns regardless of the "real" cpu instruction set being emulated. Signed-off-by: Richard Henderson --- alpha-dis.c | 4 ---- dis-asm.h | 3 +++ disas.c | 2 +- 3 files changed, 4 insertions(+), 5 deletions(-) diff --git a/alpha-dis.c b/alpha-dis.c index 8a2411e..ae331b3 100644 --- a/alpha-dis.c +++ b/alpha-dis.c @@ -238,10 +238,6 @@ extern const unsigned alpha_num_operands; #define AXP_REG_SP 30 #define AXP_REG_ZERO 31 -#define bfd_mach_alpha_ev4 0x10 -#define bfd_mach_alpha_ev5 0x20 -#define bfd_mach_alpha_ev6 0x30 - enum bfd_reloc_code_real { BFD_RELOC_23_PCREL_S2, BFD_RELOC_ALPHA_HINT diff --git a/dis-asm.h b/dis-asm.h index 296537a..5b07d7f 100644 --- a/dis-asm.h +++ b/dis-asm.h @@ -184,6 +184,9 @@ enum bfd_architecture #define bfd_mach_sh5 0x50 bfd_arch_alpha, /* Dec Alpha */ #define bfd_mach_alpha 1 +#define bfd_mach_alpha_ev4 0x10 +#define bfd_mach_alpha_ev5 0x20 +#define bfd_mach_alpha_ev6 0x30 bfd_arch_arm, /* Advanced Risc Machines ARM */ #define bfd_mach_arm_unknown 0 #define bfd_mach_arm_2 1 diff --git a/disas.c b/disas.c index 223606c..d208c52 100644 --- a/disas.c +++ b/disas.c @@ -205,7 +205,7 @@ void target_disas(FILE *out, target_ulong code, target_ulong size, int flags) disasm_info.mach = bfd_mach_sh4; print_insn = print_insn_sh; #elif defined(TARGET_ALPHA) - disasm_info.mach = bfd_mach_alpha; + disasm_info.mach = bfd_mach_alpha_ev6; print_insn = print_insn_alpha; #elif defined(TARGET_CRIS) if (flags != 32) {