diff mbox series

[22/22] gpio: xilinx: Add support for no initialisation at probe

Message ID 5D23E7CAADD3BE4A97642792FFC691C561C7A618@MBX215.d.ethz.ch
State New
Headers show
Series None | expand

Commit Message

Hedges Alexander July 21, 2018, 2:39 p.m. UTC 
From: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Date: Thu, 3 May 2018 14:35:46 +0530

Add a dt property to indicate no initialisation at probe.
In some cases the user may want no initialisation of the
gpios. For example PS only reset the user may not want the
re-initialisation of the ip.

Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Alexander Hedges <ahedges@ethz.ch>
(cherry picked from commit 184f4682479b34d279d8fec236126b7e2f6a94ce)
---
 drivers/gpio/gpio-xilinx.c | 21 ++++++++++++++-------
 1 file changed, 14 insertions(+), 7 deletions(-)
diff mbox series

Patch

diff --git a/drivers/gpio/gpio-xilinx.c b/drivers/gpio/gpio-xilinx.c
index 674f94d13251..ec017c1640b2 100644
--- a/drivers/gpio/gpio-xilinx.c
+++ b/drivers/gpio/gpio-xilinx.c
@@ -58,6 +58,7 @@ 
  * @offset: GPIO channel offset
  * @irq_base: GPIO channel irq base address
  * @irq_enable: GPIO irq enable/disable bitfield
+ * @no_init: No intitialisation at probe
  * @gpio_lock: Lock used for synchronization
  * @irq_domain: irq_domain of the controller
  * @clk: clock resource for this driver
@@ -69,6 +70,7 @@  struct xgpio_instance {
 	u32 offset;
 	int irq_base;
 	u32 irq_enable;
+	bool no_init;
 	spinlock_t gpio_lock;
 	struct irq_domain *irq_domain;
 	struct clk *clk;
@@ -243,11 +245,16 @@  static void xgpio_save_regs(struct of_mm_gpio_chip *mm_gc)
 {
 	struct xgpio_instance *chip =
 	    container_of(mm_gc, struct xgpio_instance, mmchip);
-
-	xgpio_writereg(mm_gc->regs + chip->offset + XGPIO_DATA_OFFSET,
-							chip->gpio_state);
-	xgpio_writereg(mm_gc->regs + chip->offset + XGPIO_TRI_OFFSET,
-							 chip->gpio_dir);
+	if (chip->no_init) {
+		chip->gpio_state = xgpio_readreg(mm_gc->regs +
+						 XGPIO_DATA_OFFSET);
+		chip->gpio_dir = xgpio_readreg(mm_gc->regs + XGPIO_TRI_OFFSET);
+	} else {
+		xgpio_writereg(mm_gc->regs + chip->offset + XGPIO_DATA_OFFSET,
+			       chip->gpio_state);
+		xgpio_writereg(mm_gc->regs + chip->offset + XGPIO_TRI_OFFSET,
+			       chip->gpio_dir);
+	}
 }
 
 /**
@@ -592,8 +599,6 @@  static int xgpio_of_probe(struct platform_device *pdev)
 	if (!chip)
 		return -ENOMEM;
 
-	platform_set_drvdata(pdev, chip);
-
 	/* Update GPIO state shadow register with default value */
 	of_property_read_u32(np, "xlnx,dout-default", &chip->gpio_state);
 
@@ -603,6 +608,8 @@  static int xgpio_of_probe(struct platform_device *pdev)
 	/* Update GPIO direction shadow register with default value */
 	of_property_read_u32(np, "xlnx,tri-default", &chip->gpio_dir);
 
+	chip->no_init = of_property_read_bool(np, "xlnx,no-init");
+
 	/* Update cells with gpio-cells value */
 	of_property_read_u32(np, "#gpio-cells", &cells);