| Message ID | ce4a04aefc9ea2e7f5c85a215f6749d63e503f20.1532079414.git.michal.simek@xilinx.com |
|---|---|
| State | Accepted |
| Commit | 7996fcca9d401437527d9e9a464cb79965c90c98 |
| Delegated to: | Michal Simek |
| Headers | show |
| Series | [U-Boot,1/2] arm: zynq: Remove fclk-enable property for cse-nor target | expand |
diff --git a/arch/arm/dts/zynq-cse-nor.dts b/arch/arm/dts/zynq-cse-nor.dts index ba6f9a1a79e3..edc8f59f6cea 100644 --- a/arch/arm/dts/zynq-cse-nor.dts +++ b/arch/arm/dts/zynq-cse-nor.dts @@ -56,7 +56,6 @@ clkc: clkc@100 { #clock-cells = <1>; compatible = "xlnx,ps7-clkc"; - fclk-enable = <0xf>; clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x",
Mini cse NOR configuration is running without PL that's why there is no reason to enable clock to PL. Signed-off-by: Michal Simek <michal.simek@xilinx.com> --- arch/arm/dts/zynq-cse-nor.dts | 1 - 1 file changed, 1 deletion(-)